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The MX6SL, SLL and ULL have DCP to replace CAAM in SoC. We have to
disable the CAAM driver for them.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add common plugin codes to call ROM's hwcnfg_setup and generate IVT2
header.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 58ffe85c25ff554c185d8f6fd8b6443f167227da)
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The single boot mode in MX7ULP will only boot up A7, the M4 is running in ROM
by checking entry from SIM0 GP register.
In this patch, We bind M4 image with u-boot.bin by allocating a section for m4 image.
So the whole image (included M4 image) will be loaded by A7 ROM into DDR. Then
when u-boot is up, it will try to load M4 image into TCML and boot it there.
Since M4 image will not be relocated in u-boot codes, we must load it during
board_f. Current implementation put it in arch_cpu_init to get M4 booted
as quick as possible.
We requires the M4 image with IVT head and padding embedded, not a RAW binary. The
image should be same as what is used for M4 QSPI boot in dual boot mode.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 04163dbd4f6190f310fff17b53b4bc7b8370ba89)
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Debug monitor will print out last failed AXI access info when
system reboot is caused by AXI access failure, only works when
debug monitor is enabled.
Enable this module on i.MX6SX.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit df6ac8531d498021ed379c74fc1847bd2cec7179)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 4f4ecdbf6fe2673b8ad117df1a4974bdb7e6aa4a)
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Use syscounter for i.MX6UL platform as default timer, not use GPT.
Add a CONFIG_GPT_TIMER for selecting GPT. Using CONFIG_SYSCOUNTER_TIMER
for selecting system counter.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 1c27c9ecf80b3cc63a7c9751ebfd11755f847b1d)
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In some cases this is absolutely required, so select this for some secure
features. This also requires migration of RSA_FREESCALE_EXP
Cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: Naveen Burmi <NaveenBurmi@freescale.com>
Cc: Po Liu <po.liu@freescale.com>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: Priyanka Jain <Priyanka.Jain@freescale.com>
Cc: Sumit Garg <sumit.garg@nxp.com>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
Cc: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Feng Li <feng.li_2@nxp.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Mingkai Hu <Mingkai.Hu@freescale.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Saksham Jain <saksham.jain@nxp.freescale.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
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Introduce USE_IMXIMG_PLUGIN Kconfig
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
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So the option can easily be selected through menuconfig.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
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To boot a auxiliary core in asymmetric multicore system, introduce the
new command "bootaux" to do it. Example of boot auxliary core from
0x70000000 where stores the boot head information that should be
parsed by auxiliary core, "bootaux 0x70000000".
Introduce Kconfig option IMX_BOOTAUX.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Introduce Resource Domain Controller support for i.MX.
Now i.MX6SX and i.MX7D supports this feature to assign masters
and peripherals to different domains.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add CONFIG_ROM_UNIFIED_SECTIONS for mx6sx and mx6ul target
platforms to resolve corresponding HAB_RVT_BASE base address,
the RVT table contains pointers to the HAB API functions in
ROM code.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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IMX_CONFIG is currently passed via the SYS_EXTRA_OPTIONS which is marked
as deprecated.
Add a new Kconfig file under arch/arm/imx-common and define the
IMX_CONFIG Kconfig in there.
Each board is supposed to provide a default value pointing to the
appropriate imximage.cfg file.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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