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* arm: dts: socfpga: Add mmc aliasMarek Vasut2015-08-08-0/+1
| | | | | | | Add alias for the SD/MMC controller, so it can be located by U-Boot OF support. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: dts: socfpga: Fix SPI aliasesMarek Vasut2015-08-08-16/+5
| | | | | | | | | | | | | The SPI aliases are completely wrong. First, they point to non-existing /spi@.* nodes instead of the correct /soc/spi@.* nodes. Second, the use ad-hoc string instead of a handle. Furthermore, they are copied multiple times in each board DTS. So fix it such that we move these into socfpga.dtsi and make them use the usual handles. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2015-08-06-232/+1530
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| * exynos: dts: Correct LDO and BUCK namingSimon Glass2015-08-06-63/+63
| | | | | | | | | | | | | | | | At present lower case is used for the regulator names in the device tree. The kernel uses upper case and U-Boot will require this also since it will move to a case-sensitive name check. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Add support for springSimon Glass2015-08-05-0/+589
| | | | | | | | | | | | | | | | | | | | Spring is the first ARM-based HP Chromebook 11. It is similar to snow and it uses the same Samsung Exynos5250 chip. But has some unusual features. Mainline support for it has lagged snow (both in kernel and U-Boot). Now that the exynos5 code is common we can support spring just by adding a device tree and a few lines of configuration. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: dts: Drop the old TPS65090 I2C nodeSimon Glass2015-08-05-16/+0
| | | | | | | | | | | | | | | | While the AP can access the main PMIC on snow, it must coordinate with the EC which also wants access. Drop the old definition, which can in principle generate collision errors. We will use the new arbitration driver instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dts: exynos: snow: Add a new node for the NXP video bridge driverSimon Glass2015-08-05-20/+16
| | | | | | | | | | | | The driver supports driver model. Add a node for snow, which needs it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dts: exynos: pit: Add a new node for the parade video bridge driverSimon Glass2015-08-05-5/+123
| | | | | | | | | | | | | | The new driver supports driver model and configuration via device tree. Add a node for pit, which needs this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dts: exynos: snow: Add memory layout descriptionSimon Glass2015-08-05-0/+53
| | | | | | | | | | | | | | Add a description of the snow memory layout to assist flashing tools which want to be able to deal with any exynos image. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: dts: Support EC tunnel and main TPS65090 regulatorSimon Glass2015-08-05-48/+297
| | | | | | | | | | | | | | | | | | On pit and pi the TPS65090 regulator is connected only to the EC and we must use a tunnel to get to it. The existing U-Boot support relies on a special driver. Add a tunnel definition so that the new device-model TPS65090 driver can be used unmodified. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: dts: Add PMIC and regulator definitionsSimon Glass2015-08-05-0/+304
| | | | | | | | | | | | | | | | Snow and smdk5250 use a max77686 PMIC. We have a driver for this, so add the relevant node to the device tree so it can be used. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * exynos: dts: Sync up I2C ports with the kernelSimon Glass2015-08-05-89/+94
| | | | | | | | | | | | | | | | The kernel uses upper case for I2C unit addresses. Follow the same convention to reduce differences. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
* | ARM: tegra: Add p2371-0000 boardStephen Warren2015-08-06-0/+60
| | | | | | | | | | | | | | | | | | | | | | P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O board. The combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA, a GPIO expansion header, and an analog audio jack. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: Add e2220-1170 boardStephen Warren2015-08-06-0/+59
|/ | | | | | | | | E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various expansion modules. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-07-29-1/+391
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| * P2571: dts: Add DT file for Tegra210 P2571 boardTom Warren2015-07-28-1/+108
| | | | | | | | | | | | Based on T124 Venice2. SDMMC1 is SD-card slot. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: Tegra210: Add support to common Tegra source/config filesTom Warren2015-07-28-0/+283
| | | | | | | | | | | | | | | | | | | | | | Derived from Tegra124, modified as appropriate during T210 board bringup. Cleaned up debug statements to conserve string space, too. This also adds misc 64-bit changes from Thierry Reding/Stephen Warren. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: zynq: Add support for zc770-xm011Michal Simek2015-07-28-0/+66
| | | | | | | | | | | | Add xm011 DTS file and related configs and configurations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Update zc770 dtsesMichal Simek2015-07-28-12/+176
| | | | | | | | | | | | | | Platform DTSes are missing content needed for platform to be able to use OF binding and DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Add zc702 pushbuttons to DT as gpio-keysMichal Simek2015-07-28-0/+21
| | | | | | | | | | | | | | | | Adds the two MIO connected pushbuttons on the zc702 board to the devicetree as a single multi-key device for us with the gpio-keys driver. Signed-off-by: Ezra Savard <ezra.savard@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Add missing interrupt for L2 pl310Michal Simek2015-07-28-0/+1
| | | | | | | | | | | | | | Add pl310 interrupt to the Zynq devicetree. Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Get rid of ps-clk-frequencyMichal Simek2015-07-28-1/+0
| | | | | | | | | | | | | | ps-clk-frequency is platform specific setting and shouldn't be the part of DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Update years in copyrightMichal Simek2015-07-28-1/+1
| | | | | | | | | | | | Trivial. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Sync zc702/zc706/zed/zybo DT with kernelMichal Simek2015-07-28-13/+715
| | | | | | | | | | | | Syncup with the latest DT from the Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Add reference to bus nodeMichal Simek2015-07-28-1/+1
| | | | | | | | | | | | | | For adding OCM memory in platform DTS is necessary to have reference to amba bus. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Add pinctrl nodeMichal Simek2015-07-28-1/+7
| | | | | | | | | | | | Add pinctrl node to DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Cleanup address-cells and size-cellsMichal Simek2015-07-28-1/+4
| | | | | | | | | | | | | | | | | | Remove unneeded address-cells form intc node because it is already setup in parent node. Add missing address-cells and size-cells to eth node to be shared for every platform DTSes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Clean up timer device tree nodesMichal Simek2015-07-28-2/+2
| | | | | | | | | | | | Separate IRQ cells from each other for easier reading. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Use the zynq binding with macbMichal Simek2015-07-28-2/+2
| | | | | | | | | | | | | | | | | | | | Use the new zynq binding for macb ethernet, since it will disable half duplex gigabit like the Zynq TRM says to do. Also allow the compatible cadence gem binding that won't disable half duplex but works otherwise. Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Fix GEM register area sizeMichal Simek2015-07-28-2/+2
| | | | | | | | | | | | | | The size of the GEM's register area is only 0x1000 bytes. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | spi: Fix zynq SPI bindingMichal Simek2015-07-28-2/+2
| | | | | | | | | | | | | | | | Zynq is using Cadence IP where binding is documented in the Linux kernel and there is no reason to use different binding. Synchronize it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Remove 222 MHz OPPMichal Simek2015-07-28-1/+0
| | | | | | | | | | | | | | | | | | | | Due to dependencies between timer and CPU frequency, only changes by powers of two are allowed. The clocksource driver prevents other changes, but with cpufreq and its governors it can result in being spammed with error messages constantly. Hence, remove the 222 MHz OPP. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Migrate UART to Cadence bindingMichal Simek2015-07-28-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | The Zynq UART is Cadence IP and the driver has been renamed accordingly. Migrate the DT to use the new binding for the UART driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Add a fixed regulator for CPU voltageMichal Simek2015-07-28-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | To silence the warning cpufreq_cpu0: failed to get cpu0 regulator: -19 from the cpufreq driver regarding a missing regulator, add a fixed regulator to the DT. Zynq does not support voltage scaling and the CPU rail should always be supplied with 1 V, hence it is added in the SOC-level dtsi. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Add missing nodes to DTSIMichal Simek2015-07-28-0/+100
| | | | | | | | | | | | Add ADC, CAN, GPIO, MC, DMA, DEVCFG, USB, Watchdog IPs to DTSI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: DT: Use the right names for nodesMichal Simek2015-07-28-10/+10
|/ | | | | | Based on SPEC you right names with addresses. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sunxi: ga10h: Enable both otg and regular usb host controllersHans de Goede2015-07-25-0/+26
| | | | | | | This allows using devices plugged into both ports of the tablet. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Remove bogus uart entry from utoo-p66 dts fileHans de Goede2015-07-25-14/+0
| | | | | | | | | | | At one point in time the utoo-p66 dts file in the kernel had a bogus uart entry, and it seems like we synced with the kernel at just the wrong moment. This commit removes the bogus uart entry, which breaks booting the utoo-p66 when DM_SERIAL=y. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: dts: UniPhier: add I2C ch4 device node for PH1-sLD3Masahiro Yamada2015-07-23-0/+9
| | | | | | This I2C device is used SoC-internally for controlling the DMD core. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: UniPhier: add device-specific compatible string for EEPROMMasahiro Yamada2015-07-23-1/+1
| | | | | | | | | | For the record, describe exactly which device of which vendor is used on this board. I2C EEPROM is bound by the generic compatible string, "i2c-eeprom", so this commit has no impact on the functionality. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* arm/dts/ls2085a: Add dts files for LS2085AQDS and LS2085ARDBHaikun Wang2015-07-20-0/+90
| | | | | | | Add dts source files for LS2085AQDS and LS2085ARDB boards. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm/dts/ls2085a: Add DSPI dts nodeHaikun Wang2015-07-20-0/+9
| | | | | | | Add DSPI controller dts node in fsl-ls2085a.dtsi Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm/dts/ls2085a: Bring in ls2085a dts files from linux kernelHaikun Wang2015-07-20-0/+120
| | | | | | | | Bring in required device tree files for ls2085a from Linux. These are initially unchanged and have a number of pieces not needed by U-Boot. Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-07-14-0/+31
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| * spi: cadence_qspi: add device tree binding docVikas Manocha2015-07-03-5/+0
| | | | | | | | | | | | | | | | This patch adds the device tree binding doc for the cadence qspi controller & also removes the not needed properties from the stv0991 device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| * spi: cadence_qspi: get sram size from device treeVikas Manocha2015-07-03-0/+2
| | | | | | | | | | | | | | | | | | sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| * stv0991: configure device tree for cadence qspi & flashVikas Manocha2015-07-03-0/+34
| | | | | | | | | | | | | | | | This patch add the device tree entry for qspi controller & spi flash memory. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* | sunxi: Adjust Ippo_q8h_v1_2_a33_1024x600 dts filename to match the upstream ↵Hans de Goede2015-07-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | kernel sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dts has been merged into the upstream Linux kernel as sun8i-a33-ippo-q8h-v1.2.dts, adjust u-boot to follow. Note we've never shipped a final u-boot version with the old name, so this is safe todo. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Add Sinlinx SinA33 defconfigChen-Yu Tsai2015-07-05-1/+2
| | | | | | | | | | | | | | | | | | | | Sinlinx SinA33 is a core/daughter board SDK kit from Sinlinx. It has the A33 SoC, USB host, USB OTG, audio input/output, LCD, camera, SDIO and GPIO headers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Sync sun8i dts files with the linux kernelChen-Yu Tsai2015-07-05-0/+147
|/ | | | | | | | | | Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2. This adds a dts file for Sinlinx SinA33 dev board, and the required changes in the .dtsi files. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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