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* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-08-5/+5
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| * dt: socfpga: Replace num-chipselect with num-csMarek Vasut2015-01-07-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This optional DT property is called 'num-cs', so repair the misnomers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssiMarek Vasut2015-01-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'. Fix the naming before we have to support both names. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | cros-ec-keyboard: Synchronize DT binding from linuxSjoerd Simons2015-01-05-113/+9
|/ | | | | | | | | | | | | | | | | | The ChromeOS EC keyboard is used by various different chromebooks. Peach pi being the third board in the u-boot tree to use it (snow and peach pit the other two). Rather then embedding the same big DT node in the peach-pi DT again, copy the dtsi snippit & bindings documentation from linux and include it in all 3 boards. This slightly changes the dt bindings in u-boot: * google,key-rows becomes keypad,num-rows * google,key-colums becomes keypad,num-colums * google,repeat-delay-ms and google,repeat-rate-ms are no longer used and replaced by hardcoded values (similar to tegra kbc) Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-01-01-4/+1288
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| * ARM: tegra: Enable PCIe on Jetson TK1Thierry Reding2014-12-18-0/+347
| | | | | | | | | | | | | | | | | | | | The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes the second root port to a miniPCIe slot. Enable the PCIe controller and the network driver to allow the device to boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: Add Tegra124 PCIe device tree nodeThierry Reding2014-12-18-0/+66
| | | | | | | | | | | | | | | | | | Add the device tree node for the PCIe controller found on Tegra124 SoCs. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: Add GIC for Tegra124Thierry Reding2014-12-18-0/+13
| | | | | | | | | | | | | | | | | | | | | | Add a device tree node for the GIC v2 found on the Cortex-A15 CPU complex of Tegra124. U-Boot doesn't use this but subsequent patches will add device tree nodes that reference it by phandle. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: Enable PCIe on BeaverThierry Reding2014-12-18-0/+245
| | | | | | | | | | | | | | | | | | | | | | | | The Beaver has an ethernet NIC connected to the PCIe bus. Enable the PCIe controller and the network device driver so that the device can boot over the network. In addition the board has a mini-PCIe expansion slot. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: Enable PCIe on CardhuThierry Reding2014-12-18-0/+362
| | | | | | | | | | | | | | | | | | | | | | The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC is available on the dock over the PCIe bus. Enable the PCIe controller and the network device driver so that the device can boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: Add Tegra30 PCIe device tree nodeThierry Reding2014-12-18-0/+74
| | | | | | | | | | | | | | | | Add the device tree node for the PCIe controller found on Tegra30 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: Add GIC for Tegra30Thierry Reding2014-12-18-0/+9
| | | | | | | | | | | | | | | | | | | | Add a device tree node for the GIC found on Tegra30. U-Boot doesn't use it directly but subsequent patches will add device tree nodes that reference it by phandle. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: Enable PCIe on TrimSliceThierry Reding2014-12-18-0/+69
| | | | | | | | | | | | | | | | | | | | The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the PCIe controller and the network driver so that the device can boot over the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: Add Tegra20 PCIe device tree nodeThierry Reding2014-12-18-0/+59
| | | | | | | | | | | | | | | | | | Add the device tree node for the PCIe controller found on Tegra20 SoCs. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: Enable XUSB pad controller on Jetson TK1Thierry Reding2014-12-18-0/+26
| | | | | | | | | | | | | | | | | | | | Add the PCIe and SATA lane configuration to the Jetson TK1 device tree, so that the XUSB pad controller can be appropriately configured. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: Add XUSB pad controller on Tegra124Thierry Reding2014-12-18-0/+10
| | | | | | | | | | | | | | | | | | | | The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA lanes. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: colibri_t30: comment style fixMarcel Ziswiler2014-12-18-4/+8
| | | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | odroid-XU3: Add entry for DTS EHCI GPIOSjoerd Simons2014-12-22-0/+4
| | | | | | | | | | | | | | | | | | Add samsung,vbus-gpio information for the XU3. This allows the usage of the EHCI controller on the XU3, which is connected to the SMSC LAN9514 chip (usb hub + network). Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Exynos5800: The Peach-Pi board does not have a Parade video bridgeSjoerd Simons2014-12-22-5/+0
| | | | | | | | | | | | | | | | | | | | Unlike the Peach-Pit board, there is no parade edp to lvds bridge on the Pi. So drop it from device-tree Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Odroid-XU3: Add support for Odroid-XU3Hyungwon Hwang2014-12-22-1/+47
| | | | | | | | | | | | | | | | | | | | | | This patch adds support for Odroid-XU3. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | ARM: UniPhier: fix property names of aliases nodes of device treesMasahiro Yamada2014-12-18-15/+15
|/ | | | | | | The property name of the "aliases" node should be "serial*" to assign a desired number for the device sequence number. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-16-36/+72
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| * arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probingStefan Roese2014-12-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct for the Designware SPI controllers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devicesStefan Roese2014-12-06-0/+28
| | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * arm: socfpga: dts: Add spi0 alias for Cadence QSPI driverStefan Roese2014-12-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsiStefan Roese2014-12-06-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This DT node is taken from the Rocketboard.org Linux repsitory. And is needed to enable (configure) the Cadence DM SPI driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * arm: socfpga: dts: Move to SPDX license identifiersStefan Roese2014-12-06-36/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The socfpga dts files are copied from the Rocketboards.org repository. In U-Boot we usually replace the full-blown license header text with the SPDX license identifiers. Lets do this for these new dts files as well. I just forgot to do this while adding the DT support for socfpga. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com>
* | dm: i2c: tegra: Convert to driver modelSimon Glass2014-12-11-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts all Tegra boards over to use driver model for I2C. The driver is adjusted to use driver model and the following obsolete CONFIGs are removed: - CONFIG_SYS_I2C_INIT_BOARD - CONFIG_I2C_MULTI_BUS - CONFIG_SYS_MAX_I2C_BUS - CONFIG_SYS_I2C_SPEED - CONFIG_SYS_I2C This has been tested on: - trimslice (no I2C) - beaver - Jetson-TK1 It has not been tested on Tegra 114 as I don't have that board. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
* | ARM: tegra: Add support for nyan-big boardAllen Martin2014-12-11-0/+366
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC. This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). The display is not currently supported, so it should boot on other nyan-based Chromebooks also, but only the device tree for nyan-big is provided here. The device tree file is from Linux but with features removed which are unlikely to be supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> (rebase, change to 'nyan-big', fix pinmux that resets nyan-big)
* | tegra: dts: Sync tegra124.dtsi with linux kernelSimon Glass2014-12-11-0/+114
| | | | | | | | | | | | | | | | | | | | Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings for pinctrl. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com>
* | dts: Bring in Chrome OS keyboard device tree definitionSimon Glass2014-12-11-0/+105
| | | | | | | | | | | | | | This will be used by nyan-big, but bring it in in a separate patch since it will be common to other boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* | ARM: UniPhier: add device tree sources for PH1-sLD3Masahiro Yamada2014-12-09-0/+186
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: UniPhier: add more device nodes to device treeMasahiro Yamada2014-12-09-15/+220
|/ | | | | | Add I2C controller and NAND controller devices. Fix indentation too. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* usb: UniPhier: support OF configurationMasahiro Yamada2014-11-28-0/+72
| | | | | | | | | If CONFIG_OF_CONTROL is defined, search device tree nodes that are compatible with "panasonic,uniphier-ehci" and take the base address from their "reg" property. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Marek Vasut <marex@denx.de>
* serial: UniPhier: support OF configurationMasahiro Yamada2014-11-28-0/+111
| | | | | | | This commit implements the ofdata_to_platdata handler for the UniPhier serial driver and adds serial device nodes to the device tree sources. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: add device tree sourcesMasahiro Yamada2014-11-28-0/+181
| | | | | | This commit adds basic device tree sources for UniPhier SoCs/boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* arm: odroid: usb: add support for usb host including ethernetSuriyan Ramasami2014-11-17-0/+11
| | | | | | | | | This change adds support for enabling the USB host features of the board. This includes the USB3503A hub and the SMC LAN9730 ethernet controller as well. Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: dts: Correct USB vbus-gpio numbering for SnowSjoerd Simons2014-11-17-2/+2
| | | | | | | | | | | | The current vbus GPIOs on snow make very little sense, their number is far above the maximum. As a result, USB doesn't work on snow. Correct the GPIO numbering so they match the current scheme for exynos5. Tested both EHCI and XHCI to correctly work after this change. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5800: Add DTS for new board Peach-PiAkshay Saraswat2014-11-17-1/+159
| | | | | | | | | | | | We have a new board Peach-Pi similar to Peach-Pit. Peach-Pi differs from Peach-Pit in configuration factors like display resolution, memory size, SoC version etc. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-11-13-0/+24
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| * arm: dts: zynq: Add digilent ZYBO board dtsPeter Crosthwaite2014-11-11-0/+24
| | | | | | | | | | | | | | | | | | It's a Zynq board similar in design to the currently supported ones. 512MB of RAM and UART1 is used. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-11-11-0/+858
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| * arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates targetStefan Roese2014-11-07-0/+858
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support. Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT. One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport. Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org>
* | dm: sunxi: Add support for serial using driver modelSimon Glass2014-11-05-0/+4
| | | | | | | | | | | | | | | | | | | | Add a driver for the designware serial UART used on sunxi. This just redirects to the normal ns16550 driver. Add a stdout-path to the device tree so that the correct UART is chosen. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | dm: sunxi: Add a new config for an FDT-based pcDuino3Simon Glass2014-11-05-0/+1
| | | | | | | | | | | | | | | | | | For now we won't want to mess with the existing configurations. Create a new one which will enable device tree and driver model. Note that this brings the device tree binary into u-boot-sunxi-with-spl.bin. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | dm: sunxi: dts: Add sun7i device tree filesSimon Glass2014-11-05-0/+1250
|/ | | | | | | | | | | These are from Linux 3.17-rc7 (commit fe82dcec). U-Boot only uses a small portion of these, but we may as well have something to look forward to. The total compiled size is about 25KB. Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* odroid: dts: fix name of included dtsiPrzemyslaw Marczak2014-10-27-1/+1
| | | | | | | Odroid is based on Exynos4412. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* odroid: dts: adjust sd cd-gpios for SD CardPrzemyslaw Marczak2014-10-27-1/+1
| | | | | | | | There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* trats2: dts: adjust gpio numbers after gpio reworkPrzemyslaw Marczak2014-10-27-3/+3
| | | | | | | | There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* trats: dts: adjust gpio numbers to new apiPrzemyslaw Marczak2014-10-27-2/+2
| | | | | | | | There is no gaps in exynos gpio enum after rework, so the gpio numbers should be adjusted to the new numbering. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-18 23:10:45 +0000