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* dts:exynos:update pinctrl size-cells and fix child regsPrzemyslaw Marczak2016-03-17-9/+9
| | | | | | | | | | | | | | | | | | | This change is required to avoid warnings about invalid size-cells defined in device-tree pinctrl nodes for Exynos. Tested on: - Odroid U3 - Odroid XU3 Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: sandbox: ti: Add SPDX license identifiers and notesSimon Glass2015-04-22-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | For some files I neglected to add a license. Rectify this: arch/arm/dts/exynos4210-pinctrl-uboot.dtsi arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi arch/arm/dts/exynos5250-pinctrl-uboot.dtsi arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi arch/arm/dts/s5pc100-pinctrl.dtsi arch/arm/dts/s5pc110-pinctrl.dtsi This file came from Linux and has no license information there, so add a comment to that effect: arch/sandbox/include/asm/bitops.h This file also came from Linux - presumably someone from TI could add the license: include/dt-bindings/pinctrl/omap.h Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Ingrid Viitanen <ingrid.viitanen@nokia.com>
* exynos4412: dts: adjust pinctrl-uboot to changed gpio orderPrzemyslaw Marczak2014-10-27-4/+1
| | | | | | | | The gpf0 offset was bad and it's now fixed. After fix gpio order in *pinctrl.dts , the gpy0 offset is not required now. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: exynos: dts: Adjust device tree files for U-BootSimon Glass2014-10-22-0/+46
The pinctrl bindings used by Linux are an incomplete description of the hardware. It is possible in most cases to determine the register address of each, but not in all cases. By adding an additional property we can fix this, and avoid adding a table to U-Boot for every single Exynos SOC. Signed-off-by: Simon Glass <sjg@chromium.org>