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* | | | keystone: init: enable UART1 to be able use it from kernelMurali Karicheri2014-06-06-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PWREMU_MGMT is not configured in the Linux generic UART driver as this register seems to be specific TI UART IP. So this needs to be enabled in u-boot to use UART1 from kernel space. Acked-By: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | | | arm:am33xx: Rework s_init and add board_early_init_fTom Rini2014-06-06-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the changes to the i2c framework (and adopting the omap24xx_i2c driver to them) we can no longer call i2c functions prior to gd having been set and cleared. When SPL booting, this is handled by setting gd to point to SRAM in s_init. However in the cases where we are loaded directly by ROM (memory mapped NOR or QSPI) we need to make use of the normal hooks to slightly delay these calls. Signed-off-by: Tom Rini <trini@ti.com>
* | | | arm:am33xx: Make dram_init call sdram_init() in some contextsTom Rini2014-06-06-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have two contexts for booting these platforms. One is SPL which is roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main, board_init_f from SPL, ... then U-Boot loads. The other is a memory-mapped XIP case (NOR or QSPI) where we do not run an SPL. In this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init, _main, regular board_init_f. In the first case s_init will set a valid gd and then be able to call sdram_init which in many cases will need i2c (which needs a valid gd for gd->cur_i2c_bus). In this second case we must (and are able to and should) defer sdram_init() into dram_init() called by board_init_f as gd will have been set in _main and cleared in board_init_f. Signed-off-by: Tom Rini <trini@ti.com>
* | | | am43xx_evm: Add qspiboot targetSourav Poddar2014-06-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ePOS EVM and EVM SK have QSPI as an option to boot. Add a qspiboot target that utilizes QSPI for env and so forth as an example of best practices. As QSPI is booted from directly we need to chang CONFIG_SYS_TEXT_BASE. Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices we need to handle that elsewhere, once NAND support is also added. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* | | | omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and ↵pekon gupta2014-06-06-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPMC_NAND_ECC_LP_x16_LAYOUT OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros to configure GPMC controller for x7 or x8 bit device connected to its interface. Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above macros can be completely removed. Signed-off-by: Pekon Gupta <pekon@ti.com>
* | | | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-02-40/+54
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| * | | Exynos: Make sure ps_hold gets set in the SPLDoug Anderson2014-05-31-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setting ps_hold ought to be one of the first things we do when we first boot up. If we wait until the main u-boot runs we won't set it in time and the PMIC may power us back off. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | exynos: Enable PSHOLD in SPLSimon Glass2014-05-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is quite a tight deadline in enabling PSHOLD, less than a second. In some cases (e.g. with USB download), U-Boot takes longer than that to load, so the board powers off before U-Boot starts. Add a call in SPL to enable PSHOLD. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | ARM: exynos: clock: modify the set_mmc_clk for exynos4Jaehoon Chung2014-05-16-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modified the mmc_set_clock for eynos4. The goal of this patch is that fsys-div register should be reset. And retore the div-value, not using the value of lowlevel_init. (For using SDMMC4, this patch is needs) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | arm: exynos: clock: Remove exynos4x12_set_mmc_clk functionBeomho Seo2014-05-16-28/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | exynos4x12_set_mmc_clk function have been removed. Because, exynos4x12_clock and exynos4_clock return same div_fsys* value. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | arm: exynos: pinmux: add sdmmc4 gpio configratuionBeomho Seo2014-05-16-6/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For use dwmmc controller at exynos4, add SDMMC4 gpio configuration. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | | ARM: at91sam9m10g45ek: enable mci0 supportWu, Josh2014-05-27-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also we enable the mmc command in configuration file. As both CONFIG_CMD_MMC and CONFIG_CMD_USB use the CONFIG_DOS_PARTITION, so remove the redundant CONFIG_DOS_PARTITION definition. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | | arm:at91: enable ROM loadable atmel imageAndreas Bießmann2014-05-27-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For sama5d3xek we need to modify the SPL image for correct detection by ROM code. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Bo Shen <voice.shen@atmel.com>
* | | | ARM: atmel: switch to main crystal osc for SPL bootBo Shen2014-05-27-0/+39
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | If without switch to main crystal oscillator, the sama5d3 SoC will use internal on chip RC oscillator. In order to get better accuracy, switch to main crystal oscillator. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | sunxi: non-FEL SPL boot support for sun7iIan Campbell2014-05-25-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for booting from an MMC card. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | sunxi: add gmac Ethernet supportIan Campbell2014-05-25-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the GMAC Ethernet controller on Allwinner A20 (sun7i) processors. Enable for the Cubietruck. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@ti.com>
* | | sunxi: add sun7i cpu, board and start of day supportIan Campbell2014-05-25-1/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds generic board, start of day and basic build system support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Signed-off-by: Adam Sampson <ats@offog.org> Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luc Verhaegen <libv@skynet.be> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Patrick Wood <patrickhwood@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Wills Wang <wills.wang.open@gmail.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | sunxi: add sun7i dram setup supportIan Campbell2014-05-25-0/+594
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DRAM initialisation support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | sunxi: add sun7i pinmux and gpio supportIan Campbell2014-05-25-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the basic pinmux and gpio support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ma Haijun <mahaijuns@gmail.com> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | sunxi: add sun7i clocks and timer support.Ian Campbell2014-05-25-0/+338
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the basic clocks and timer support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Some of the code here is common to multiple sunxi subarchtectures, hence files are named sun4i which is the earliest similar variant. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | Arm64 fix a bug of vbar_el3 initializationDavid Feng2014-05-25-2/+2
| |/ |/| | | | | Signed-off-by: David Feng <fenghua@phytium.com.cn>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-05-24-141/+212
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| * | am33xx: report silicon revision instead of codeSergey Alyoshin2014-05-23-18/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | As revision code 1 is for silicon revision 2.0, it is easily confused with silicon revision 1.0. Device type report also reworked in same style. Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com>
| * | ARM: OMAP: Fix omap_sdram_size calculationLokesh Vutla2014-05-23-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Last section of DMM is used for trapping tiler unmapped sections. Corresponding trap_size should be deducted from total SDRAM size only if trap section is overlapping with available SDRAM based on DMM sections. Fixing the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | armv7:TI: Add <asm/ti-common/sys_proto.h> and migrate omap_hw_init_contextTom Rini2014-05-23-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The omap_hw_init_context function (and assorted helpers) is the same for all OMAP-derived parts as when CHSETTINGS are used, that's the same and our DDR base is also always the same. In order to make this common we simply need to update the names of the define for DDR address space which is also common. Cc: Sricharan R. <r.sricharan@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: DRA7xx: ctrl: Fix efuse register addressesLokesh Vutla2014-05-23-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Efuse register addresses are wrongly programmed. Fixing the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * | ARM: DRA72x: Update EMIF dataLokesh Vutla2014-05-23-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | DRA72 has 1GB connected to EMIF1 only. Updating the details. And also enable WA for BUG0039 only if corresponding EMIF is present. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * | ARM: DRA72x: clocks: Update the hwdataLokesh Vutla2014-05-23-0/+7
| | | | | | | | | | | | | | | | | | | | | Adding the prcm, dplls, control module hooks for DRA72x. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * | ARM: DRA72x: volt: Update the pmic offsetsKeerthy2014-05-23-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | TPS65917 is used in DRA722 evm. Update the address offsets accordingly. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * | ARM: DRA72x: Add Silicon ID supportLokesh Vutla2014-05-23-0/+3
| | | | | | | | | | | | | | | | | | | | | Add silicon ID code for DRA722 silicon. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * | ARM: omap: merge GPMC initialization code for all platformpekon gupta2014-05-23-110/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPMC controller on TI's OMAP SoC is general purpose controller to interface with different types of external devices like; - parallel NOR flash - parallel NAND flash - OneNand flash - SDR RAM - Ethernet Devices like LAN9220 Though GPMC configurations may be different for each platform depending on clock-frequency and external device interfacing with controller. But initialization sequence remains common across all platfoms. Thus this patch merges gpmc_init() scattered in different arch-xx/mem.c files into single omap-common/mem-common.c However, actual platforms specific register config values are still sourced from corresponding platform specific headers like; AM33xx: arch/arm/include/asm/arch-am33xx/mem.h OMAP3: arch/arm/include/asm/arch-omap3/mem.h OMAP4: arch/arm/include/asm/arch-omap4/mem.h OMAP4: arch/arm/include/asm/arch-omap5/mem.h Also, CONFIG_xx passed by board-profile decide config for which set of macros need to be used for initialization CONFIG_NAND: initialize GPMC for NAND device CONFIG_NOR: initialize GPMC for NOR device CONFIG_ONENAND: initialize GPMC for ONENAND device Signed-off-by: Pekon Gupta <pekon@ti.com> [trini: define GPMC_SIZE_256M for omap3] Signed-off-by: Tom Rini <trini@ti.com>
* | | Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'Albert ARIBAUD2014-05-23-1/+1
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| * | | arm: rmobile: r8a7791: Fix MOD_SEL3 function table about FN_SEL_IEBNobuhiro Iwamatsu2014-05-21-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | FN_SEL_IEB is assigned 2bit, and 2bit can represent 4 patterns. However FN_SEL_IEB but we only use 3. It adds empty patterns as 0. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* | | Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'Albert ARIBAUD2014-05-23-8/+112
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| * | zynq: treat ps7_init.c/h as external files to ignore themMasahiro Yamada2014-05-14-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ps7_init.c and ps7_init.h are supposed to be exported by hw project and copied to board/xilinx/zynq/ directory. We want them to be ignored by git. So what we should do is to always treat them as external files rather than replacing ps7_init.c This commit does: - Move a weak function ps7_init() to arch/arm/cpu/armv7/zynq/spl.c and delete board/xilinx/zynq/ps7_init.c - Compile board/xilinx/zynq/ps7_init.c only when it exists - Add .gitignore to ignore ps7_init.c/h Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: ehci: Added USB host driver supportMichal Simek2014-05-14-0/+24
| | | | | | | | | | | | | | | | | | | | | Added USB host driver for zynq. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Add MIO detection codeMichal Simek2014-05-14-0/+50
| | | | | | | | | | | | | | | | | | | | | Add run-time MIO pin detection to get actual pin configuration for specific periphery. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Setup correct slcr_lock valueMichal Simek2014-05-14-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | The driver should setup slcr state according to slcr operations. Reported-by: Andrey Filippov <andrey@elphel.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: slcr: Fix incorrect commentaryMichal Simek2014-05-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fix c&p error in zynq_slcr_devcfg_enable() commentary and extending it with description according to Zynq TRM also in zynq_slcr_devcfg_disable(). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Call zynq board_init() in SPLMichal Simek2014-05-14-0/+7
| | | | | | | | | | | | | | | | | | Call board_init() if SPL is configured with CONFIG_SPL_BOARD_INIT. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | ARM: zynq: Do not use half memory size for ECC caseMichal Simek2014-05-14-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Memory size should be specified without ECC place. If you need to have half memory size, please change u-boot configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Added efuse status register base addressSiva Durga Prasad Paladugu2014-05-14-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added efuse status register base address. This register is used for determining whether efuse was blown or not. Also, added the zynq_get_silicon_version() to get the silicon version of the zynq board. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Fix sparse warning in ddrc.cMichal Simek2014-05-14-1/+1
| | | | | | | | | | | | | | | | | | | | | Warning: arch/arm/cpu/armv7/zynq/ddrc.c:43:24: warning: Using plain integer as NULL pointer Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Fix sparse warnings in slcr.cMichal Simek2014-05-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Warnings: arch/arm/cpu/armv7/zynq/slcr.c:21:6: warning: symbol 'zynq_slcr_lock' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:27:6: warning: symbol 'zynq_slcr_unlock' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:34:6: warning: symbol 'zynq_slcr_cpu_reset' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:54:6: warning: symbol 'zynq_slcr_gem_clk_setup' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:81:6: warning: symbol 'zynq_slcr_devcfg_disable' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:94:6: warning: symbol 'zynq_slcr_devcfg_enable' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:107:5: warning: symbol 'zynq_slcr_get_boot_mode' was not declared. Should it be static? arch/arm/cpu/armv7/zynq/slcr.c:113:5: warning: symbol 'zynq_slcr_get_idcode' was not declared. Should it be static? Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge remote-tracking branch 'u-boot-sh/rmobile'Albert ARIBAUD2014-05-16-64/+50
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | Conflicts: boards.cfg Trivial conflict, maintainer change plus board addition
| * | arm: rmobile: Update print_cpuinfo functionNobuhiro Iwamatsu2014-04-28-27/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | The print_cpuinfo fucntion has same code. It has a code of many common. This adds a table of CPU information, duplicate using for-loop. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: Add rmobile_get_cpu_rev_fraction() for R-Car SoCsNobuhiro Iwamatsu2014-04-28-0/+5
| | | | | | | | | | | | | | | | | | | | | This adds rmobile_get_cpu_rev_fraction to get fraction revision for R-Car SoCs. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: Add 1 to value of the CPU revision in ↵Nobuhiro Iwamatsu2014-04-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rmobile_get_cpu_rev_integer() Value that can be obtained in the rmobile_get_cpu_rev_integer() starts at 0. However, revisions to start from 1, which adds 1. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: Merge functions to get the CPU information of R8A7790 and R8A7791Nobuhiro Iwamatsu2014-04-28-34/+4
| | | | | | | | | | | | | | | | | | | | | | | | Functions to get the CPU information of R8A7790 and R8A7791 are common. This merges these as cpu_info-rcar.c. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: r8a779x: Fix L2 cache init and latency settingNobuhiro Iwamatsu2014-04-28-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | L2CTLR only need to update for cluster 0. This changes L2CTLR to initialize only when cluster is 0. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
generated by cgit v1.1 at 2024-11-01 05:22:17 +0000