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* imx: ddr: drop duplicated debug infoPeng Fan2016-01-03-1/+0
| | | | | | | Drop duplicated debug info for tcl. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6: add missing return valueJeroen Hofstee2015-12-07-0/+2
| | | | | | | cc: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* ARM: mxs: fix VDDD brownout settingMichael Heimpold2015-12-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment, the desired brownout is at 1.0V. However, this setting cannot be realized by hardware since we have only 3 bits to represent the voltage difference from the target value. Target value is 1500 mV, brownout target is 1000 mV, voltage steps are 25 mV. Register content calculation: (1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) = 0x14 Register takes only 3 bits, that is 0x4. But 0x4 * 25 [mV] = 100 [mV], that means that actual brownout level is 1500 [mV] - 100 [mV] = 1.4 V. Minimum possible BO level is 1500 [mV] - 0x7 * 25 [mV] = 1315 [mV]. So lets use this value as desired BO value (which is also the same as FSL bootlets use). Signed-off-by: Michael Heimpold <mhei@heimpold.de> Cc: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* mx6: clock: Modify GPMI clock to support mx6sxYe.Li2015-11-25-0/+12
| | | | | | | On mx6sx, the CCM register bits for GPMI are different as other mx6 platforms. Modify the GPMI clock function to support mx6sx. Signed-off-by: Ye.Li <B37916@freescale.com>
* cgtqmx6eval: Add SPL supportOtavio Salvador2015-11-25-0/+3
| | | | | | | | | Congatec has several MX6 boards based on quad, dual, dual-lite and solo. Add SPL support so that all the variants can be supported Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* zynqmp: mp: Add support for booting R5 from any addressMichal Simek2015-11-19-3/+35
| | | | | | | Put jump trampoline to TCM at 0 and setup R5 reset address to 0. Jump trampoline ensures that jump to the right location. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* spl: mmc: add support for BOOT_DEVICE_MMC2Nikita Kiryanov2015-11-18-9/+1
| | | | | | | | | | | Currently the mmc device that SPL looks at is always mmc0, regardless of the BOOT_DEVICE_MMCx value. This forces some boards to implement hacks in order to boot from other mmc devices. Make SPL take into account the correct mmc device. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com>
* spl: change return values of spl_*_load_image()Nikita Kiryanov2015-11-18-1/+3
| | | | | | | | | | | | | | | | | | | | | | | Make spl_*_load_image() functions return a value instead of hanging if a problem is encountered. This enables main spl code to make the decision whether to hang or not, thus preparing it to support alternative boot devices. Some boot devices (namely nand and spi) do not hang on error. Instead, they return normally and SPL proceeds to boot the contents of the load address. This is considered a bug and is rectified by hanging on error for these devices as well. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans De Goede <hdegoede@redhat.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* board: ti: beagle_x15: Rename to indicate support for TI am57xx evmsKipisz, Steven2015-11-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BeagleBoard X15 (http://beagleboard.org/x15) support in u-boot does actually support two different platform configuration offered by TI. In addition to BeagleBoard X15, it also supports the TMDXEVM5728 (or more commonly known as AM5728-evm). Information about the TI AM57xx EVM can be found here http://www.ti.com/tool/tmdxevm5728 The EVM configuration is 1-1 compatible with BeagleBoard X15 with the additional support for mPCIe, mSATA, LCD, touchscreen, Camera, push button and TI's wlink8 offering. Hence, we rename the beagle_x15 directory to am57xx to support TI EVMs that use the AM57xx processor. By doing this we have common code reuse. This sets the stage to have a common u-boot image solution for multiple TI EVMs such as that already done for am335x and am437x. This sets the stage for upcoming multiple TI EVMs that share the same code base. NOTE: Commit eae7ae185335 ("am437x: Add am57xx_evm_defconfig using CONFIG_DM") introduced DT support for beagle_x15 under am57xx_evm platform name. However, this ignored the potential confusion arising for users as a result. To prevent this, existing beagle_x15_defconfig is renamed as am57xx_evm_nodt_defconfig to denote that this is the "non device tree" configuration for the same platform. We still retain am57xx-beagle-x15.dts at this point, since we just require the common minimum dts. As a result of this change, users should expect changes in build procedures('make am57xx_evm_nodt_defconfig' instead of 'make beagle_x15_defconfig'). Hopefully, this would be a one-time change. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
* imx: mx6: implement reset_miscPeng Fan2015-11-12-0/+7
| | | | | | | | We need to power down lcdif before uboot reset to make reset can pass stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6: add clock api for lcdifPeng Fan2015-11-12-0/+245
| | | | | | | | | Implement mxs_set_lcdclk, enable_lcdif_clock and enable_pll_video. The three API can be used to configure lcdif related clock when CONFIG_VIDEO_MXS enabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* mxs: add parameter base_addr for mxs_set_lcdclkPeng Fan2015-11-12-1/+1
| | | | | | | | | | | Change mxs_set_lcdclk prototype to add a new parameter base_addr. There are two LCD interfaces for i.MX6SX, we may support LCDIF1 or LCDIF2. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* mx7: psci: add basic psci supportPeng Fan2015-11-12-0/+136
| | | | | | | | | | | | 1. add basic psci support for imx7 chip. 2. support cpu_on and cpu_off. 3. switch to non-secure mode when boot linux kernel. 4. set csu allow accessing all peripherial register in non-secure mode. Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* arm: discard relocation entries for secure textPeng Fan2015-11-12-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code such as PSCI in section named secure is bundled with u-boot image, and when bootm, the code will be copied to their runtime address same to compliation/linking address - CONFIG_ARMV7_SECURE_BASE. When compile the PSCI code and link it into the u-boot image, there will be relocation entries in .rel.dyn section for PSCI. Actually, we do not needs these relocation entries. If still keep the relocation entries in .rel.dyn section, r0 at line 103 and 106 in arch/arm/lib/relocate.S may be an invalid address which may not support read/write for one SoC. 102 /* relative fix: increase location by offset */ 103 add r0, r0, r4 104 ldr r1, [r0] 105 add r1, r1, r4 106 str r1, [r0] So discard them to avoid touching the relocation entry in arch/arm/lib/relocate.S. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Tom Warren <twarren@nvidia.com> Cc: York Sun <yorksun@freescale.com> Cc: Hans De Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> Cc: Jan Kiszka <jan.kiszka@siemens.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Merge git://git.denx.de/u-bootStefano Babic2015-11-12-302/+760
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| * Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-11-10-2/+21
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| | * armv8: allow custom MMU setup routines on ARMv8Stephen Warren2015-11-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order for noncached_init() to operate correctly, SoCs must set up a custom page table with fine-grained (2MiB) sections, which can be configured from noncached_init(). This is currently performed by arch/arm/cpu/armv8/{fsl-lsch3,zynqmp}/cpu.c by cut/pasting and re-implementing mmu_setup, enable_caches(), etc. There are some other reasons for the duplication there though, such as enabling icache early, and enabling dcaching earlier with a different configuration. This change makes mmu_setup() a weak implementation, so that the MMU setup code can be replaced without having to duplicate other code that calls it. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| | * arm: stm32f4: fix a bug when a random sector gets erasedVadzim Dambrouski2015-11-10-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Old sector number is not being cleared from FLASH_CR register. For example when first erased sector was 001 and then you want to erase sector 010, sector 011 gets erased instead. This patch clears old sector number from FLASH_CR register before a new one is written. Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
| | * arm: stm32f4: fix a bug when only first sector gets erasedVadzim Dambrouski2015-11-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | flash_lock call is inside a for loop, so after the first iteration flash is locked and no more sectors can be erased. Move flash_lock out of the loop. Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
| | * arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILDAlbert ARIBAUD2015-11-10-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD, some files fail to build, most of the time because they include mcr instructions, which only exist for Thumb-2. This patch introduces a Kconfig option CONFIG_THUMB2 and uses it to select between Thumb-2 and ARM mode for the aforementioned files. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * | Various Makefiles: Add SPDX-License-Identifier tagsTom Rini2015-11-10-0/+4
| |/ | | | | | | | | | | | | | | | | | | | | After consulting with some of the SPDX team, the conclusion is that Makefiles are worth adding SPDX-License-Identifier tags too, and most of ours have one. This adds tags to ones that lack them and converts a few that had full (or in one case, very partial) license blobs into the equivalent tag. Cc: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Tom Rini <trini@konsulko.com>
| * s5p: cpu_info: print "cpu-model" if exists in dtsPrzemyslaw Marczak2015-11-02-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU name for Exynos was concatenated with cpu id, but for new Exynos platforms, like Chromebook Peach Pi based on Exynos5800, the name of SoC variant does not include the real SoC cpu id (0x5422). For such case, the CPU name should be defined in device tree. This commit introduces new device-tree property for Exynos: - "cpu-model" - with cpu name string If defined, then the cpu id is not printed. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * arm: ls1021a: Add sata support on qds and twr boardtang yuantian2015-10-29-0/+43
| | | | | | | | | | | | | | | | | | | | Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls1021aqds and ls1021atwr boards. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043a: Enable secondary coresHou Zhiqiang2015-10-29-0/+14
| | | | | | | | | | | | | | | | | | | | After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to make secondary cores excute in spin loop. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardbYangbo Lu2015-10-29-1/+21
| | | | | | | | | | | | | | | | This patch adds esdhc support for ls1043ardb. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043a: Add Fman supportShaohui Xie2015-10-29-0/+41
| | | | | | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: Add nand boot supportGong Qianyu2015-10-29-0/+3
| | | | | | | | | | | | | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: Add LS1043ARDB board supportMingkai Hu2015-10-29-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
| * armv8/fsl_lsch2: Add fsl_lsch2 SoCMingkai Hu2015-10-29-0/+299
| | | | | | | | | | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl_lsch3: Change arch to fsl-layerscapeMingkai Hu2015-10-29-302/+212
| | | | | | | | | | | | | | | | | | | | | | | | | | There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: enable snooping for CAAM transactionshoria.geanta@freescale.com2015-10-29-0/+3
| | | | | | | | | | | | | | | | | | | | | | Enable snooping for CAAM read & write transactions by programming the SCFG snoop configuration register: SCFG_SNPCNFGCR[SECRDSNP] SCFG_SNPCNFGCR[SECWRSNP] Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ls102xa: fdt: Disable IFC in SD boot for QSPIAlison Wang2015-10-29-1/+1
| | | | | | | | | | | | | | | | | | As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled in SD boot for QSPI. This patch will add fdt support for this rule. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: fdt: Check the pointer returned from call to a function may ↵Alison Wang2015-10-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | be NULL Pointer 'reg' returned from call to function 'fdt_getprop' may be NULL, will be passed to function and may be dereferenced there by passing argument 1 to function 'of_read_number'. So check pointer 'reg' first. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | arm: imx: add secure boot fuse details for imx7 SoCAdrian Alonso2015-10-30-0/+8
| | | | | | | | | | | | | | Add secure boot fuse details (location) bank = 1, word = 3; for imx7 SoC platforms. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | arm: imx: add secure boot fuse details for imx6 SoCAdrian Alonso2015-10-30-0/+8
| | | | | | | | | | | | | | Add secure boot fuse details (location) bank = 0, word = 6; for imx6 SoC platforms. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | imx: hab: rework unified rom section for mx7Adrian Alonso2015-10-30-0/+2
| | | | | | | | | | | | | | Rework unified section macro select via Kconfig option instead of macro definition in mx7_common header file. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | imx: hab: use unified rom section for mx6sx and mx6ulAdrian Alonso2015-10-30-0/+2
| | | | | | | | | | | | | | | | | | Add CONFIG_ROM_UNIFIED_SECTIONS for mx6sx and mx6ul target platforms to resolve corresponding HAB_RVT_BASE base address, the RVT table contains pointers to the HAB API functions in ROM code. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | imx: hab: rework secure boot support for imx6Adrian Alonso2015-10-30-503/+0
| | | | | | | | | | | | | | Rework secure boot support for imx6, move existing hab support for imx6 into imx-common for SoC reuse. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | imx: cpu: move common chip revision id'sAdrian Alonso2015-10-30-0/+1
|/ | | | | | | Move common chip revision id's to main cpu header file mx25 generic include cpu header for chip revision Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* omap-common: Common get_board_serial function to pass serial through ATAGPaul Kocialkowski2015-10-22-0/+18
| | | | | | | | | Since there is a common function to grab the serial number from the die id bits, it makes sense have one to parse that serial number and feed it to the serial ATAG. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap-common: Common function to display die id, replacing omap3-specific versionPaul Kocialkowski2015-10-22-23/+11
| | | | | | | | | This introduces omap_die_id_display to display the full die id. There is no need to store it in an environment variable, that no boot script is using anyway. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap-common: Common serial and usbethaddr functions based on die idPaul Kocialkowski2015-10-22-22/+27
| | | | | | | | | Now that we have a common prototype to grab the omap die id, functions to figure out a serial number and usb ethernet address can use it directly. Those also get an omap_die_id prefix for better consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap5: omap_die_id supportPaul Kocialkowski2015-10-22-0/+12
| | | | | | | | This introduces omap5 support for omap_die_id, which matches the common omap_die_id definition. It replaces board-specific code to grab the die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap4: omap_die_id supportPaul Kocialkowski2015-10-22-1/+12
| | | | | | | | This introduces omap4 support for omap_die_id, which matches the common omap_die_id definition. It replaces board-specific code to grab the die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap3: omap_die_id supportPaul Kocialkowski2015-10-22-9/+6
| | | | | | | | This replaces the previous get_dieid definition with omap_die_id, that matches the common omap_die_id definition. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap-common: Common omap_die_id definitionPaul Kocialkowski2015-10-22-0/+5
| | | | | | | | This introduces a common definition for omap_die_id, that aims at providing a common interface for accessing omap platform's die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* sunxi: board: Only try to use the MMC related functions if enabledMaxime Ripard2015-10-20-1/+5
| | | | | | | | | | | So far, even if CONFIG_MMC was not enabled the board code was trying to use the MMC-related functions, resulting in linker errors. Protect those calls by an ifdef. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: power: Unify axp pmic function namesHans de Goede2015-10-20-11/+2
| | | | | | | | | Stop prefixing the axp functions for setting voltages, etc. with the model number, there ever is only one pmic driver built into u-boot, this allows simplifying the callers. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Switch to using malloc_simple for the splHans de Goede2015-10-20-0/+1
| | | | | | | | | | common/dlmalloc.c is quite big, both in .text and .data usage. E.g. for a Mele_M9 sun6i board build this reduces .text from 0x4214 to 0x3b94 bytes, and .data from 0x54c to 0x144 bytes. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Tom Rini <trini@konsulko.com>
* armv8/mmu: Set bits marked RES1 in TCRThierry Reding2015-10-15-3/+3
| | | | | | | | | | | For EL3 and EL2, the documentation says that bits 31 and 23 are reserved but should be written as 1. For EL1, only bit 23 is not reserved, so only write bit 31 as 1. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.1 at 2024-12-28 17:15:41 +0000