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* MLK-12416-9: mx6qp: define CONFIG_MX6QPPeng Fan2017-04-05-0/+3
| | | | | | | | Define CONFIG_MX6QP which will also set CONFIG_MX6Q, otherwise plugin code will use wrong ddr script. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 901d9eb01736ab54822678a197fe1aeb281a81b9)
* MLK-12493-1 Add support for various boot deviceYe Li2017-04-05-0/+4
| | | | | | | | | | Add support for various boot devices like NAND, QSPINOR, SPINOR, eMMC, EIMNOR, SATA. Modify board level files to support the feature and add corresponding defconfig files Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 72c35e80b86f7f75a52db45959793882bb730793)
* MLK-12495 mx6: Add LDO bypass supportYe Li2017-04-05-2/+149
| | | | | | | | | | | | | | | | Port LDO bypass support from v2015 to support the features: 1. Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz, enable LDO bypass and setup PMIC voltages. LDO bypass is dependent on the flatten device tree file. 2. We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to reboot whole board, so split these code to independent function so that board file can call it freely. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 5b87d04dba66fa45375d59648838ef89f559f75d)
* MLK-13307-7 imx: mx6sll: update soc settingsPeng Fan2017-04-05-2/+11
| | | | | | | Update soc settings for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit afa2d78f2b799337eae3dc67c0ed702d5520eee6)
* MLK-14259-3 mx6ulevk: Add support for NANDYe Li2017-04-05-0/+13
| | | | | | | Add NAND pinmux settings, clock setting and related configurations. Default not enabled, need hardware rework. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12565 mx7: rdc: Change IS_ENABLED to remove build warningYe Li2017-04-05-2/+3
| | | | | | | | Change to use #ifdef not the IS_ENABLED, because we will get build warning when the CONFIG_IMX_RDC is not set. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit a212eff242efb8dc171479cbaca34049d508f87b)
* MLK-10708 imx:mx6qp Update Saturation THR for PRExPeng Fan2017-04-05-4/+4
| | | | | | | | | | Update settings for PRE. Value for Saturation THR of PREx, changed from 0x20 to 0x10 to make system more stable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 02e7090604e55d9690532294b02b499609d46e63) (cherry picked from commit f7c5cf580fcc2c8ab95a8d835f5874d26216910f) (cherry picked from commit 1a90b60731cd60feba1ef7a11ede2613283bb4a8)
* MLK-12483-4 mx6: Modify drivers to disable fused modulesYe Li2017-04-05-9/+8
| | | | | | | | | | | Add the fuse checking in drivers, when the module is disabled in fuse, the driver will not work. Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C, USB-EHCI, GIS, LCDIF. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
* MLK-12483-3 mx6: Add a module fuse checkingYe Li2017-04-05-1/+278
| | | | | | | | | | | | | | | | Implement a functionality to read the soc fuses and check if any module is fused. For fused module, we have to disable it in u-boot dynamically, and change the its node in FDT to "disabled" status before starting the kernel. In this patch, we implement the ft_system_setup for FDT fixup. This function will be called during boot process or by "fdt systemsetup" command. To enable the module fuse checking, two configurations must be defined: CONFIG_MODULE_FUSE CONFIG_OF_SYSTEM_SETUP Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 7236051526b73a5a25cc8330a79f5c08b7d70726)
* MLK-10674-2 imx: mx6qp settings for PREPeng Fan2017-04-05-2/+31
| | | | | | | | | | | | | | | | | | | | | | | Since the following piece settings can not be in DCD table, we add them in enable_ipu_clock. " setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0 setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1 setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2 setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3 setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0 setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1 setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2 setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE " CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h, the settings sure will effect. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 61cec88a59ebf450dd1352d81e03b5aa842e1d71) (cherry picked from commit 3d25e2acd48f605678a98cf594a715809dea8286)
* MLK-10576 ARM: i.MX6: exclude the ARM errata from i.MX6 UP systemNitin Garg2017-04-05-5/+0
| | | | | | | | | | | | | | | | | The ARM errata 751472, 794072, 761320, 845369 only applied to the following configuration: This erratum affects configurations with either: - One processor if the ACP is present - Two or more processors i.MX6 family does not have the ACP and thus only the MPCore system will be impacted, which are the i.MX6DQ, i.MX6DL, and i.MX6QP. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit 0db960784ba4f631ee5c0321b5d25f3b1ac55640) (cherry picked from commit 850f27d137a083a141c99fe9828d596807937d38)
* MLK-10524: iMX6x: Implement workaround for Cortex-A9 errata 845369Nitin Garg2017-04-05-0/+7
| | | | | | | | | | | Under very rare timing circumstances, transitioning into streaming mode might create a data corruption. Present on Two or more processors or 1 core with ACP, all revisions. This erratum can be worked round by setting bit[22] of the undocumented Diagnostic Control Register to 1. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 70ad44e523680de67dd8b7a7505d7f27799980ee) (cherry picked from commit f20a65847577ff40dc7e3739a0bb69926885c734)
* ENGR00325255 pcie:enable pcie support on imx6sx sdYe Li2017-04-05-5/+32
| | | | | | | | | | | | | | | | | Enable pcie support in uboot on imx6sx sd boards - enable_pcie_clock should be call before ssp_en is set, since that ssp_en control the phy_ref clk gate, turn on it after the source of the pcie clks are stable. - add debug info - add rx_eq of gpr12 on imx6sx - there are random link down issue on imx6sx. It's pcie ep reset issue. solution:reset ep, then retry link can fix it. (cherry picked from commit ec78595a24b5ff1020baa97b6d6e79a3a3326307) Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 81fd30250110d72992758f08b66c07306126892b)
* ENGR00319965 pcie: mask the imx6sl outRichard Zhu2017-04-05-15/+20
| | | | | | | | | | imx6sl doesn't have the pcie module, mask the pcie related codes from imx6sl. Signed-off-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit acaff11da33f8f0cb1521d3c48e64e7ed9a87bec) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 48a4606ef575c72e16e31c167dce042fcb66191c)
* ENGR00319415 pcie: random link down issue after warm-rstRichard Zhu2017-04-05-0/+18
| | | | | | | | | | | | | | | | | | | | | There are about 0.02% percentage on some imx6q/dl/solo hw boards, random pcie link down when warm-reset is used. Make sure to clear the ref_ssp_en bit16 of gpr1 before warm-rst, and set ref_ssp_en after the pcie clks are stable to workaround it. rootcause: * gpr regisers wouldn't be reset by warm-rst, while the ref_ssp_en is required to be reset by pcie. (work-around in u-boot) * ref_ssp_en should be set after pcie clks are stable. (work-around in kernel) Signed-off-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit 5cc825b12c6b86a22f1a6a0535b52cf3ee142e77) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 6193cf4e3384a59e29546d13a67657f7faeafc9e) (cherry picked from commit 7b4aabeddffabca46d7d6e7ef2611de468a6b4f7)
* MLK-11064 imx: mx6qp: Adjust AQos settings for peripheralsYe.Li2017-04-05-0/+3
| | | | | | | | | | | To resolve USB camera bandwidth issue, the patch sets recommended AQoS setting from IC team value for peripheral and only on imx6qp. The address is: 0xbb0608, the value is: 0x80000201 Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 11906c712a52e7a20caf71d7c5da4e951a59db29) (cherry picked from commit 5dcf073b8f2479a2adbb8d9fb03d9c9c70664e32)
* MLK-12534 mx6: shutdown vddpu and PCIE phy to save powerYe Li2017-04-05-0/+42
| | | | | | | | | | | | | | | | | | | Shutdown VDDPU and PCIE phy to save power. For PCIE, the i.MX6SL and i.MX6UL does not have this module, so don't need it. For VDDPU, the i.MX6UL does not have GPU, does not need it. And on i.MX6QP there is narrow window that PRE driver is ready but GPU driver probe later, and the later GPU driver turn on PU may cause 'PRE hang' issue. To simplify thing, do not turn off PU in u-boot. Reference: commit: 6b0787b726e2ff32210d742d93ecd3f4bb2ae402 commit: 4bd0032c0eba50fa0caf43f50f735a3cfbe36a8d Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 5c96ea91fe89c67991c929c9b39ffaa940d28391)
* MLK-12533 mx6sx: select OSC as uart's clk parentYe Li2017-04-05-0/+13
| | | | | | | | | | | As M4 is sourcing UART clk from OSC, to make UART work when M4 is enabled, need to select OSC as clk parent, 24M OSC is enough for debug UART in uboot. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Anson Huang <b20788@freescale.com> (cherry picked from commit b5e1b393192099e91c5cb75b69291c87eacb9f60) (cherry picked from commit 416dea861c2dd5a197bf2354069bba8415a20b12)
* ENGR00321299 gis: clean csi0 input mux set bit in GPRSandor Yu2017-04-05-0/+6
| | | | | | | | | | | | When gis enable in uboot, the CSI0 input mux select setting to vadc module, clean the bit when gis disabled. Signed-off-by: Sandor Yu <R01008@freescale.com> (cherry picked from commit ae66b17b7da3be50dc81ca636b67e8e879f52e26) (cherry picked from commit c83fd326e810c2fff44b8b02e78406d5d04c977c) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit d6e803ed5f51d31ebe7e9d178aa11f16401b7fc8) (cherry picked from commit 2065b417ae93436736e49ca66b66aa0791d003fe)
* ENGR00315894-77 mx6 soc: Add vadc power up/down functionYe.Li2017-04-05-0/+46
| | | | | | | | | | | Add vadc power up/down function. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 96d990ef754a879f6ca9da4adf6e0be3d21cdc51) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 01b88201aa86bef26a4254ac43aff90e99fd2c06) (cherry picked from commit d50b53f138dd3b4c463c80ac8e14f41ac0fdd415)
* ENGR00315894-76 mx6 clock: Add vadc clock enable functionYe.Li2017-04-05-0/+12
| | | | | | | | | | | Add vadc clock enable function. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 721c7a1448c5b7265b597b83d18f8338a27ea213) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 903a59ef941f39b6d7f693dd7c60528e166de079) (cherry picked from commit dc767fb7d5c155f2a6ef01c4dee808b9c1944fc2)
* MLK-12437-1 mx6sx: Add support for LVDS displayYe Li2017-04-05-1/+60
| | | | | | | | The i.MX6SX uses a LVDS bridge to mux to the LCDIF interface. Implmement a function for this muxing. So that on 6SX we can use a LVDS display. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 763658d9b497e44b7411581da592ef5b522e9cc9)
* ENGR00315894-70 iMX6SX:Video Update MXS LCDIF driverYe.Li2017-04-05-1/+1
| | | | | | | | | | | | | | | Add a new interface "mxs_lcd_panel_setup" to setup fb parameters and specifies the LCDIF controller for multiple controllers of iMX6SX. Pass fb parameters via "videomode" env remains work if the new interface is not called before video initialization. Modify LCDIF clock interface "mxs_set_lcdclk" to support multiple LCDIF controllers on iMX6SX. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit d7f49b9378547c3a57b96bcdb907fc44616beb3d) (cherry picked from commit e1343191b9de227c582847e7eeb5ce9238be0754)
* MLK-12434-9: mx6: define CONFIG_BOARD_LATE_INITPeng Fan2017-04-05-0/+5
| | | | | | | | Define CONFIG_BOARD_LATE_INIT for mx6qarm2/mx6slevk/mx6sxsabresd to let mmcdev/mmcroot work as expected. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 86135fb7e55c3046ead899b83f58dd6048eda9e8)
* MLK-11528 imx: mx6ul check fuse before init beePeng Fan2017-03-14-1/+11
| | | | | | | | | | | | Need to check fuse bit 25 of bank 0 word 4 before initialize bee. The bit: 0 means bee enabled, 1 means bee disabled. If disabled, continuing initialize bee will cause system hang, so need to check this bit before initialize bee. Add macro to enable BEE in header file, default disabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit ef4cb7c53418e4e1dd7cfcb7c6974cfea77ef3c0)
* MLK-10958 imx: mx6ul support Bus Encryption EnginePeng Fan2017-03-14-1/+463
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to support Bus Encryption Engine(BEE) for i.MX 6UL. Supported feature: 1. SNVS key and soft key 2. CTR and ECB mode 3. Specify address region to bee. Two commands are included: bee init [key] [mode] [start] [end] - BEE block initial "Example: bee init 1 1 0x80000000 0x80010000\n" bee test [region] "Example: bee test 1\n" Mapping: [0x10000000 - (0x10000000 + size - 1)] : [start - (start + size - 1)] [0x30000000 - (0x30000000 + IRAM_SIZE - 1)] : [IRAM_BASE_ADDR - (IRAM_BASE_ADDR + IRAM_SIZE - 1)] Whatever start is, start - (start + size -1) will be fixed mapping to 0x10000000 - (0x10000000 + size - 1) Since default AES region's protected size is SZ_512M, so on mx6ul evk board, you can not simply run 'bee init', it will overlap with uboot execution environment, you can use 'bee init 0 0 0x80000000 0x81000000'. If want to use bee, Need to define CONFIG_CMD_BEE in board configuration header file, since CONFIG_CMD_BEE default is not enabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 29b9bdbbdac9678dba9b7bc2d3662598e9c548a5) (cherry picked from commit 6d45292ff7e7020a48842f033f8a337daabe4476)
* MLK-14422 imx7d: wdog: Overwrite the reset_cpu to turn off internal reset signalYe Li2017-03-14-0/+15
| | | | | | | | Set wdog WCR register SRS bit to turn off internal reset signal WDOG_RESET_B_DEB for mx7d. So that the warm reset is disabled. The WDA is cleared to output WDOG_B immediately to reset the board. Signed-off-by: Ye Li <ye.li@nxp.com>
* ARM: Migrate errata to KconfigTom Rini2017-03-09-0/+8
| | | | | | | | | This moves all of the current ARM errata from various header files and in to Kconfig. This allows for a minor amount of cleanup as we had some instances where both a general common header file was enabling errata as well as the board config. We now just select these once at the higher level in Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* flash: complete CONFIG_SYS_NO_FLASH move with renamingMasahiro Yamada2017-02-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We repeated partial moves for CONFIG_SYS_NO_FLASH, but this is not completed. Finish this work by the tool. During this move, let's rename it to CONFIG_MTD_NOR_FLASH. Actually, we have more instances of "#ifndef CONFIG_SYS_NO_FLASH" than those of "#ifdef CONFIG_SYS_NO_FLASH". Flipping the logic will make the code more readable. Besides, negative meaning symbols do not fit in obj-$(CONFIG_...) style Makefiles. This commit was created as follows: [1] Edit "default n" to "default y" in the config entry in common/Kconfig. [2] Run "tools/moveconfig.py -y -r HEAD SYS_NO_FLASH" [3] Rename the instances in defconfigs by the following: find . -path './configs/*_defconfig' | xargs sed -i \ -e '/CONFIG_SYS_NO_FLASH=y/d' \ -e 's/# CONFIG_SYS_NO_FLASH is not set/CONFIG_MTD_NOR_FLASH=y/' [4] Change the conditionals by the following: find . -name '*.[ch]' | xargs sed -i \ -e 's/ifndef CONFIG_SYS_NO_FLASH/ifdef CONFIG_MTD_NOR_FLASH/' \ -e 's/ifdef CONFIG_SYS_NO_FLASH/ifndef CONFIG_MTD_NOR_FLASH/' \ -e 's/!defined(CONFIG_SYS_NO_FLASH)/defined(CONFIG_MTD_NOR_FLASH)/' \ -e 's/defined(CONFIG_SYS_NO_FLASH)/!defined(CONFIG_MTD_NOR_FLASH)/' [5] Modify the following manually - Rename the rest of instances - Remove the description from README - Create the new Kconfig entry in drivers/mtd/Kconfig - Remove the old Kconfig entry from common/Kconfig - Remove the garbage comments from include/configs/*.h Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-02-03-24/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/ls1046aqds_defconfig configs/ls1046aqds_nand_defconfig configs/ls1046aqds_qspi_defconfig configs/ls1046aqds_sdcard_ifc_defconfig configs/ls1046aqds_sdcard_qspi_defconfig configs/ls1046ardb_emmc_defconfig configs/ls1046ardb_qspi_defconfig configs/ls1046ardb_sdcard_defconfig
| * arch: arm: update the IFC IP input clockPrabhakar Kushwaha2017-02-03-24/+5
| | | | | | | | | | | | | | | | | | | | | | | | IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: Enable workaround for erratum A-008336York Sun2017-01-31-0/+1
| | | | | | | | | | | | | | Erratum A-008336 applies to LS1046A per latest SoC document. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2017-02-01-1/+214
|\ \
| * | BOARD: MCCMON6: Provide support for iMX6q based mccmon6 boardLukasz Majewski2017-01-30-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | This patch provides u-boot support for Liebherr (LWN) mccmon6 board. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | ARM: imx6ul: Move liteSOM source to SoC directoryMarcin Niestroj2017-01-27-1/+209
| |/ | | | | | | | | | | | | | | | | | | | | Moving arch/arm/mach-litesom/ to arch/arm/cpu/armv7/mx6/ was requested in [1] during discussion of chiliSOM support patches. [1] http://lists.denx.de/pipermail/u-boot/2017-January/279137.html Suggested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm64: spin-table: add more information in Kconfig helpMasahiro Yamada2017-01-28-2/+4
|/ | | | | | | | | | | | | | | | | | | | | This feature seems to be sometimes misunderstood. The intention is: [1] Bring the slaves into the U-Boot proper image, not SPL (unless you have a special reason to do otherwise). [2] The operation must be done in a board (SoC) specific manner since how to wake the slaves from the Boot ROM is SoC specific. [3] The slaves must enter U-Boot proper after U-Boot relocates itself because the "cpu-release-addr" property points to the relocated memory area. [2] is already explained in the help. We can make [1] even clearer by mentioning "U-Boot proper" instead of "U-Boot". [3] is missing, so I am adding it to the list. Instead, "before the master CPU jumps to the kernel" is a matter of course, so removed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Convert CONFIG_BOARD_EARLY_INIT_F to KconfigSimon Glass2017-01-25-0/+8
| | | | | | | This converts the following to Kconfig: CONFIG_BOARD_EARLY_INIT_F Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_ARCH_EARLY_INIT_R to KconfigSimon Glass2017-01-25-0/+4
| | | | | | | This converts the following to Kconfig: CONFIG_ARCH_EARLY_INIT_R Signed-off-by: Simon Glass <sjg@chromium.org>
* Kconfig: Migrate BOARD_LATE_INIT to a selectTom Rini2017-01-24-0/+34
| | | | | | | | | This option should not really be user selectable. Note that on PowerPC we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be conditional on that. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
* status_led: Kconfig migrationUri Mashiach2017-01-21-17/+18
| | | | | | | | | | | | | Move all of the status LED feature to drivers/led/Kconfig. The LED status definitions were moved from the board configuration files to the defconfig files. TBD: Move all of the definitions in the include/status_led.h to the relevant board's defconfig files. Tested boards: CL-SOM-AM57x, CM-T335 Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
* serial, ns16550: bugfix: ns16550 fifo not enabledHeiko Schocher2017-01-20-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor" breaks u-boot commandline working with long commands sending to the board. Since the above patch, you have to setup the fcr register. For board/archs which enable OF_PLATDATA, the new field fcr in struct ns16550_platdata is not filled with a default value ... This leads in not setting up the uarts fifo, which ends in problems, when you send long commands to u-boots commandline. Detected this issue with automated tbot tests on am335x based shc board. The error does not popup, if you type commands. You need to copy&paste a long command to u-boots commandshell (or send a long command with tbot) Possible boards/plattforms with problems: ./arch/arm/cpu/arm926ejs/lpc32xx/devices.c ./arch/arm/mach-tegra/board.c ./board/overo/overo.c ./board/quipos/cairo/cairo.c ./board/logicpd/omap3som/omap3logic.c ./board/logicpd/zoom1/zoom1.c ./board/timll/devkit8000/devkit8000.c ./board/lg/sniper/sniper.c ./board/ti/beagle/beagle.c ./drivers/serial/serial_rockchip.c Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-01-19-79/+1012
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| * kconfig: fsl PPA: move CONFIG_* to KconfigHou Zhiqiang2017-01-18-2/+26
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCIHou Zhiqiang2017-01-18-14/+14
| | | | | | | | | | | | | | | | Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * kconfig: armv8: move armv8 sec_firmware CONFIG_* to KconfigHou Zhiqiang2017-01-18-3/+36
| | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York S: clean up scripts/config_whitelist.txt] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: aarch64: Fix the warning about x1-x3 nonzero issueAlison Wang2017-01-18-32/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI nodeWenbin Song2017-01-18-0/+157
| | | | | | | | | | | | | | | | | | | | The default MSI node in kernel tree is for LS1043A rev1.0 silicon, if rev1.1 silicon used, need to fixup the MSI node to match it. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/ls1043a: fixup GIC offset for ls1043a rev1Wenbin Song2017-01-18-5/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-lsch3: enable snoopable sata read and writeTang Yuantian2017-01-18-0/+2
| | | | | | | | | | | | | | | | | | By default the SATA IP on the ls208Xa SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl_lsch2: Add chip power supply voltage setupHou Zhiqiang2017-01-18-0/+361
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set up chip power supply voltage according to voltage ID. The fuse status register provides the values from on-chip voltage ID fuses programmed at the factory. These values define the voltage requirements for the chip. Main operations: 1. Set up the core voltage 2. Set up the SERDES voltage and reset SERDES lanes 3. Enable/disable DDR controller support 0.9V if needed Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-11-01 12:18:41 +0000