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* Consolidate bootcount code into drivers/bootcountStefan Roese2012-09-01-85/+1
| | | | | | | | | | | | | | | | | | | This patch moves all bootcount implementations into a common directory: drivers/bootcount. The generic bootcount driver is now usable not only by powerpc platforms, but others as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Christian Riesch <christian.riesch@omicron.at> Cc: Manfred Rudigier <manfred.rudigier@omicron.at> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de> Tested-by: Valentin Longchamp <valentin.longchamp@keymile.com> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* EXYNOS: PINMUX: Add pinmux support for I2CRajeshwari Shinde2012-07-31-0/+52
| | | | | | | This patch adds pinmux code for I2C. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* EXYNOS: CLK: Add i2c clockRajeshwari Shinde2012-07-31-0/+33
| | | | | | | | | This adds i2c clock information for EXYNOS5. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* imx-common: add i2c.c for bus recovery supportTroy Kisky2012-07-31-1/+142
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* i.mx: iomux-v3.c: move to imx-common directoryTroy Kisky2012-07-31-2/+2
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* i.mx: iomux-v3.h: move to imx-common include directoryTroy Kisky2012-07-31-1/+1
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* iomux-v3: remove include of mx6x_pins.hTroy Kisky2012-07-31-1/+0
| | | | | | | This include is not needed. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Jason Liu <r64343@freescale.com>
* ARM1136: Fix cache range checksBenoît Thébaudeau2012-07-21-3/+3
| | | | | | | | | | | | | | bad_cache_range actually returned true if the range was OK, but it was used according to its name, which resulted in all valid dcache range invalidate/flush operations being dropped. Hence, most DMA transfers resulted in garbage data. This patch renames this function according to what it does, and it fixes the interpretation of its return value by other functions. The chosen naming is the same as for ARM926EJ-S in order to be consistent. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Stefano Babic <sbabic@denx.de>
* arm: armv7: add compile option -mno-unaligned-access if availableTetsuyuki Kobayashi2012-07-20-0/+2
| | | | | | | | | | Recent compiler generates unaligned memory access in armv7 default. But current U-Boot does not allow unaligned memory access, so it causes data abort exception. This patch add compile option "-mno-unaligned-access" if it is available. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Tested-by: Gary Thomas <gary@mlbassoc.com>
* arm: Fix to mistake clean the memory spaceZhong Hongbo2012-07-20-40/+65
| | | | | | | | | | | In currently, when __bss_start is equal to __bss_end__, The bss loop will clear all the things in memory space. But just only when __bss_end__ greater than __bss_start__, we do the clear bss section operation. Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2012-07-10-2/+89
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: tegra: define fdt_load/fdt_high variables tegra: enable bootz command tegra: usb: Fix device enumeration problem of USB1 tegra: trimslice: set up serial flash pinmux tegra: add pin_mux_spi() board initialization function tegra: add GMC/GMD funcmux entry for SFLASH tegra: bootcmd: start USB only when needed tegra: bootcmd enhancements tegra: add enterrcm command tegra: enable CONFIG_ENV_VARS_UBOOT_CONFIG Add env vars describing U-Boot target board tegra: usb: fix wrong error check tegra: add ULPI on USB2 funcmux entry tegra: fix leftover CONFIG_TEGRA2_MMC & _SPI build switches tegra: Add Tamonten Evaluation Carrier support tegra: Use SD write-protect GPIO on Tamonten tegra: Implement gpio_early_init() on Tamonten tegra: Allow boards to perform early GPIO setup tegra: plutux: Add device tree support tegra: medcom: Add device tree support tegra: Rework Tamonten support beagle: add eeprom expansion board info for bct brettl4 Signed-off-by: Wolfgang Denk <wd@denx.de>
| * tegra: add GMC/GMD funcmux entry for SFLASHStephen Warren2012-07-09-0/+10
| | | | | | | | | | | | | | This is used on TrimSlice. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: add enterrcm commandStephen Warren2012-07-09-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's boot ROM supports a mode whereby code may be downloaded and flash programmed over a USB connection. On dev boards, this is typically entered by holding down a "force recovery" button and resetting the CPU. However, not all boards have such a button (one example is the Compulab Trimslice), so a method to enter RCM from software is useful. This change implements the command "enterrcm" to do this, and enables it for all Tegra boards by default. Even on boards other than Trimslice, controlling this over a UART may be useful, e.g. to allow simple remote control without the need for mechanical button actuators, or hooking up relays/... to the button. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: usb: fix wrong error checkLucas Stach2012-07-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | loop_count runs down from 10000, so the correct condition to error out is ==0. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Tom Warren <twarren.nvidia@gmail.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: add ULPI on USB2 funcmux entryLucas Stach2012-07-09-1/+12
| | | | | | | | | | | | | | | | | | | | | | This is needed as a prerequisite for Tegra USB ULPI support within U-Boot. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | EXYNOS: Fix USB compiler warningRajeshwari Shinde2012-07-10-1/+0
| | | | | | | | | | | | | | Fixed the compiler warning message. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Marek Vasut <marex@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2012-07-09-0/+44
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-usb: CONFIG: EXYNOS5: USB: Enable USB 2.0 on smdk5250 EXYNOS5: USB: Fix incorrect USB base addresses EXYNOS: Add power Enable/Disable for USB-EHCI USB: EXYNOS: Set USB 2.0 HOST Link mode EXYNOS5: Add structure for PMU registers EXYNOS5: Fix system register structure USB: EXYNOS: Incorporate EHCI review comments Signed-off-by: Wolfgang Denk <wd@denx.de>
| * EXYNOS: Add power Enable/Disable for USB-EHCIRajeshwari Shinde2012-07-09-0/+22
| | | | | | | | | | | | | | | | | | This patch adds functions to enable/disable the power of USB host controller for EXYNOS5. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
| * USB: EXYNOS: Set USB 2.0 HOST Link modeRajeshwari Shinde2012-07-09-0/+22
| | | | | | | | | | | | | | This patch adds a function to set usb host mode to USB 2.0 HOST Link for EXYNOS5 Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
* | Revert "arm: bugfix: save_boot_params_default accesses uninitalized stack ↵Wolfgang Denk2012-07-09-7/+1
|/ | | | | | | | | | | when -O0" This reverts commit fa042186b932e9b9ee9a2fd8a04a3acf7c70d224. It causes build warnings like this: cpu.c:48:1: warning: -fstack-usage not supported for this target [enabled by default] Signed-off-by: Wolfgang Denk <wd@denx.de>
* ARM: mx28: Remove CONFIG_ARCH_CPU_INITFabio Estevam2012-07-07-2/+0
| | | | | | | | | No need to define CONFIG_ARCH_CPU_INIT. All mx28 based boards should use arch_cpu_init(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* No need to define CONFIG_ARCH_CPU_INIT.Fabio Estevam2012-07-07-2/+0
| | | | | | | All mx6 based boards should use arch_cpu_init(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* SPL: ARM: spear: Add SPL support for SPEAr600 platformStefan Roese2012-07-07-7/+1480
| | | | | | | | | | | | This patch adds SPL support for SPEAr600. Currently only SNOR (Serial NOR) flash support is included. Other boot devices (NAND, MMC, USB ...) may be added with later patches. Tested on the STM SPEAr600 evaluation and x600 SPEAr600 boards. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Amit Virdi <amit.virdi@st.com> Cc: Vipin Kumar <vipin.kumar@st.com>
* SPEAr: explicitly select clk src for UARTShiraz Hashim2012-07-07-1/+6
| | | | | | | | | | UART in u-boot intends to run on 48MHz clock supplied by USB PLL. Explicitly select the intended clock source. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* SPEAr: Add basic arch related support for SPEAr SoCsVipin KUMAR2012-07-07-1/+84
| | | | | | | | | | | Earlier, architecture specific init code was mixed with board initialization code in board/spear/... This patch updates architecture support for SPEAr in latest u-boot and prints the SoC information. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0Tetsuyuki Kobayashi2012-07-07-1/+7
| | | | | | | | save_boot_params_default() in cpu.c accesses uninitialized stack area when it compiled with -O0 (not optimized). Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Tom Rini <trini@ti.com>
* ARM: OMAP4/5: Move USB clocks to essential group.SRICHARAN R2012-07-07-9/+7
| | | | | | | | | USB clocks will be required for fastboot, tftp related functionalities. Move these clocks to essential group inorder to have the functionality working when non-essential clocks are not enabled. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP4/5: Move gpmc clocks to essential group.SRICHARAN R2012-07-07-2/+2
| | | | | | | | | | GPMC clocks are currently getting enabled as a part non-essential clocks. This will be required during NOR boot. Move this to essential group to keep the functionality, when non-essential clocks are not enabled. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP4+: Move external phy initialisations to arch specific place.SRICHARAN R2012-07-07-27/+37
| | | | | | | | | | The external phy is present in the case OMAP5 soc is currently configured in emif-common.c. This results in having dummy structures for those Socs which do not have a external phy. So by having a weak function in emif-common and overriding it in OMAP5, avoids the use of dummy structures. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* omap4: Use a smaller M,N couple for IVA DPLLSebastien Jan2012-07-07-1/+1
| | | | | | | | | | This reduced M,N couple corresponds to the advised value from TI HW team. Tested on 4460 Pandaboard, it also provides peripheral clocks closer to the advised values. Signed-off-by: Sebastien Jan <s-jan@ti.com>
* omap: emif: fix bug in manufacturer code testSteve Sakoman2012-07-07-1/+1
| | | | | | | Code currently tests for <= 0xff. Micron manufacturer code is 0xff, so Micron memory will not be detected! Signed-off-by: Steve Sakoman <steve@sakoman.com>
* omap: emif: deal with rams that return duplicate mr data on all byte lanesSteve Sakoman2012-07-07-1/+6
| | | | | | | | | | Some rams (Micron for example) return duplicate mr data on all byte lanes. Users of the get_mr function currently don't deal with this duplicated data gracefully. This patch detects the duplicated data and returns only the expected 8 bit mr data. Signed-off-by: Steve Sakoman <steve@sakoman.com>
* OMAP4+: Force DDR in self-refresh after warm resetLokesh Vutla2012-07-07-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Errata ID:i727 Description: The refresh rate is programmed in the EMIF_SDRAM_REF_CTRL[15:0] REG_REFRESH_RATE parameter taking into account frequency of the device. When a warm reset is applied on the system, the OMAP processor restarts with another OPP and so frequency is not the same. Due to this frequency change, the refresh rate will be too low and could result in an unexpected behavior on the memory side. Workaround: The workaround is to force self-refresh when coming back from the warm reset with the following sequence: • Set EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2 • Set EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM to 0x0 • Do a dummy read (loads automatically new value of sr_tim) This will reduce the risk of memory content corruption, but memory content can't be guaranteed after a warm reset. This errata is impacted on OMAP4430: 1.0, 2.0, 2.1, 2.2, 2.3 OMAP4460: 1.0, 1.1 OMAP4470: 1.0 OMAP5430: 1.0 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
* OMAP4+: Handle sdram init after warm resetLokesh Vutla2012-07-07-4/+6
| | | | | | | | | | EMIF and DDR device state are preserved in warmreset. Redoing the full initialisation would cause unexpected behaviour. Do only partial initialisation to account for frequency change. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
* ARM: OMAP3+: Detect reset typeLokesh Vutla2012-07-07-0/+5
| | | | | | | | | | | | Certain modules are not affected by means of a warm reset and need not be configured again. Adding an API to detect the reset reason warm/cold. This will be used to skip the module configurations that are retained across a warm reset. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com>
* arm: bugfix: Move vector table before jumping relocated codeTetsuyuki Kobayashi2012-07-07-0/+12
| | | | | | | | | | Interrupts and exceptions doesn't work in relocated code. It badly use IRQ_STACK_START_IN in rom area as interrupt stack. It is because the vecotr table is not moved to ram area. This patch moves vector table before jumping relocated code. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Tested-by: Tom Rini <trini@ti.com>
* kirkwood: add save functionality kirkwood_mpp_conf functionValentin Longchamp2012-07-07-1/+9
| | | | | | | | | | | | | | If a second non NULL argument is given to the kirkwood_mpp_conf function, it will be used to store the current configuration of the MPP registers. mpp_save must be a preallocated table of the same size as mpp_list and it must be zero terminated as well. A later call to kirkwood_mpp_conf function with this saved list as first (mpp_conf) argment will set the configuration back. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
* i.MX6 USDHC: Use the ESDHC clockMichael Langer2012-07-07-0/+4
| | | | | | | | | | | | | | | The commit "i.mx: fsl_esdhc: add the i.mx6q support" (4692708d) introduces support for the i.MX6Q MMC host controller USDHC. MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock of the ESDHC IP found in < i.MX6 silicon. However, the default clock for the USDHC IP found in i.MX6 is 200MHz (MXC_ESDHC_CLK). This difference will cause a 3 times higher clock on SD_CLK than expected (see fsl_esdh.c -> set_sysctl()). Signed-off-by: Michael Langer <michael.langer@de.bosch.com> CC: Stefano Babic <sbabic@denx.de> CC: Jason Liu <r64343@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX28: Add function to adjust memory parametersMarek Vasut2012-07-07-0/+8
| | | | | | | | | | | | | | This function can be overridden at run-time and allows implementors of new boards based on the i.MX28 chip to fine-tune the memory params. It is possible to write into the dram_vals array because when the SPL runs, it is located SRAM. Therefore the location is writable. There is no possibility of these data to be read-only. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
* mx53: Fix mask for SATA reference clockFabio Estevam2012-07-07-1/+1
| | | | | | | | SATA_ALT_REF_CLK field corresponds to bits 1 and 2 of offset 0x180c. Fix the mask for these bits. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* EXYNOS5: PINMUX: Added default pinumx settingsRajeshwari Shinde2012-07-07-1/+221
| | | | | | | | | | | | | This patch performs the pinmux configuration in a common file. As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is supported. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: fix cpuinfo and cpu detectingMinkyu Kang2012-07-07-2/+3
| | | | | | | | | | Since Exynos architecture have new SoCs, need to fix cpuinfo correctly. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Cc: Chander Kashyap <chander.kashyap@linaro.org>
* OMAP5: Change voltages for omap5432Lokesh Vutla2012-07-07-10/+21
| | | | | | Change voltages for OMAP5432 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: DPLL core lock for OMAP5432Lokesh Vutla2012-07-07-6/+15
| | | | | | | No need to Unlock DPLL initially. DDR3 can work at normal OPP from initialozation Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: EMIF: Add support for DDR3 deviceLokesh Vutla2012-07-07-3/+122
| | | | | | | | | In OMAP5432 EMIF controlller supports DDR3 device. This patch adds support for ddr3 device intialization and configuration. Initialization sequence is done as specified in JEDEC specs. This also adds support for ddr3 leveling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: ADD precalculated timings for ddr3Lokesh Vutla2012-07-07-1/+50
| | | | | | | Adding precalculated timings for ddr3 with 1cs adding required registers for ddr3 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: Configure the io settings for omap5432 uevm boardLokesh Vutla2012-07-07-19/+79
| | | | | | This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: ADD chip detection for OMAP5432 SOCLokesh Vutla2012-07-07-1/+9
| | | | | | This patch adds chip detection for OMAP5432 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* DaVinci: fix ddr2 vtp i/o calibrationTroy Kisky2012-07-07-4/+3
| | | | | | | | | | | | | | | | | | | | | Previously, only the low 5 bits (NCH) were being transfered from DDRVTPR to DDRVTPIOCR, the bits 5-9 where zeroed. VTP_RECAL should be bit 15, not 18. The only mainline board affected by this change is davinci_sonata. The other Davinci boards define CONFIG_SKIP_LOWLEVEL_INIT. However, if the program that loads u-boot on these boards copied the code from u-boot, they will need fixed as well. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Please get tested by acks before applying, where tested by means an overnight memory test. Thanks Troy
* ARM: OMAP5: Align memory used for testing to the power of 2SRICHARAN R2012-07-07-0/+3
| | | | | | | | | | | | get_ram_size checks the given memory range for valid ram, but expects the size of memory to be aligned to the power of 2. In case of OMAP5 evm board the memory available is 2GB - 16MB(used for TRAP section) = 2032MB. So always ensure that the size of memory used for testing is aligned to the power of 2. Signed-off-by: R Sricharan <r.sricharan@ti.com>
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