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* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-11-10-2/+21
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| * armv8: allow custom MMU setup routines on ARMv8Stephen Warren2015-11-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order for noncached_init() to operate correctly, SoCs must set up a custom page table with fine-grained (2MiB) sections, which can be configured from noncached_init(). This is currently performed by arch/arm/cpu/armv8/{fsl-lsch3,zynqmp}/cpu.c by cut/pasting and re-implementing mmu_setup, enable_caches(), etc. There are some other reasons for the duplication there though, such as enabling icache early, and enabling dcaching earlier with a different configuration. This change makes mmu_setup() a weak implementation, so that the MMU setup code can be replaced without having to duplicate other code that calls it. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * arm: stm32f4: fix a bug when a random sector gets erasedVadzim Dambrouski2015-11-10-0/+3
| | | | | | | | | | | | | | | | | | | | Old sector number is not being cleared from FLASH_CR register. For example when first erased sector was 001 and then you want to erase sector 010, sector 011 gets erased instead. This patch clears old sector number from FLASH_CR register before a new one is written. Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
| * arm: stm32f4: fix a bug when only first sector gets erasedVadzim Dambrouski2015-11-10-1/+1
| | | | | | | | | | | | | | | | flash_lock call is inside a for loop, so after the first iteration flash is locked and no more sectors can be erased. Move flash_lock out of the loop. Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
| * arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILDAlbert ARIBAUD2015-11-10-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD, some files fail to build, most of the time because they include mcr instructions, which only exist for Thumb-2. This patch introduces a Kconfig option CONFIG_THUMB2 and uses it to select between Thumb-2 and ARM mode for the aforementioned files. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | Various Makefiles: Add SPDX-License-Identifier tagsTom Rini2015-11-10-0/+4
|/ | | | | | | | | | | After consulting with some of the SPDX team, the conclusion is that Makefiles are worth adding SPDX-License-Identifier tags too, and most of ours have one. This adds tags to ones that lack them and converts a few that had full (or in one case, very partial) license blobs into the equivalent tag. Cc: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* s5p: cpu_info: print "cpu-model" if exists in dtsPrzemyslaw Marczak2015-11-02-1/+13
| | | | | | | | | | | | | | | | | | | | The CPU name for Exynos was concatenated with cpu id, but for new Exynos platforms, like Chromebook Peach Pi based on Exynos5800, the name of SoC variant does not include the real SoC cpu id (0x5422). For such case, the CPU name should be defined in device tree. This commit introduces new device-tree property for Exynos: - "cpu-model" - with cpu name string If defined, then the cpu id is not printed. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: ls1021a: Add sata support on qds and twr boardtang yuantian2015-10-29-0/+43
| | | | | | | | | | Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls1021aqds and ls1021atwr boards. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043a: Enable secondary coresHou Zhiqiang2015-10-29-0/+14
| | | | | | | | | | After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to make secondary cores excute in spin loop. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardbYangbo Lu2015-10-29-1/+21
| | | | | | | | This patch adds esdhc support for ls1043ardb. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043a: Add Fman supportShaohui Xie2015-10-29-0/+41
| | | | | | | | Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043ardb: Add nand boot supportGong Qianyu2015-10-29-0/+3
| | | | | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043ardb: Add LS1043ARDB board supportMingkai Hu2015-10-29-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
* armv8/fsl_lsch2: Add fsl_lsch2 SoCMingkai Hu2015-10-29-0/+299
| | | | | | | | | | | Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/fsl_lsch3: Change arch to fsl-layerscapeMingkai Hu2015-10-29-302/+212
| | | | | | | | | | | | | There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls102xa: enable snooping for CAAM transactionshoria.geanta@freescale.com2015-10-29-0/+3
| | | | | | | | | | | Enable snooping for CAAM read & write transactions by programming the SCFG snoop configuration register: SCFG_SNPCNFGCR[SECRDSNP] SCFG_SNPCNFGCR[SECWRSNP] Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ls102xa: fdt: Disable IFC in SD boot for QSPIAlison Wang2015-10-29-1/+1
| | | | | | | | | As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled in SD boot for QSPI. This patch will add fdt support for this rule. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/fsl-lsch3: fdt: Check the pointer returned from call to a function may ↵Alison Wang2015-10-26-1/+1
| | | | | | | | | | | | be NULL Pointer 'reg' returned from call to function 'fdt_getprop' may be NULL, will be passed to function and may be dereferenced there by passing argument 1 to function 'of_read_number'. So check pointer 'reg' first. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* omap-common: Common get_board_serial function to pass serial through ATAGPaul Kocialkowski2015-10-22-0/+18
| | | | | | | | | Since there is a common function to grab the serial number from the die id bits, it makes sense have one to parse that serial number and feed it to the serial ATAG. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap-common: Common function to display die id, replacing omap3-specific versionPaul Kocialkowski2015-10-22-23/+11
| | | | | | | | | This introduces omap_die_id_display to display the full die id. There is no need to store it in an environment variable, that no boot script is using anyway. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap-common: Common serial and usbethaddr functions based on die idPaul Kocialkowski2015-10-22-22/+27
| | | | | | | | | Now that we have a common prototype to grab the omap die id, functions to figure out a serial number and usb ethernet address can use it directly. Those also get an omap_die_id prefix for better consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap5: omap_die_id supportPaul Kocialkowski2015-10-22-0/+12
| | | | | | | | This introduces omap5 support for omap_die_id, which matches the common omap_die_id definition. It replaces board-specific code to grab the die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap4: omap_die_id supportPaul Kocialkowski2015-10-22-1/+12
| | | | | | | | This introduces omap4 support for omap_die_id, which matches the common omap_die_id definition. It replaces board-specific code to grab the die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap3: omap_die_id supportPaul Kocialkowski2015-10-22-9/+6
| | | | | | | | This replaces the previous get_dieid definition with omap_die_id, that matches the common omap_die_id definition. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap-common: Common omap_die_id definitionPaul Kocialkowski2015-10-22-0/+5
| | | | | | | | This introduces a common definition for omap_die_id, that aims at providing a common interface for accessing omap platform's die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* sunxi: board: Only try to use the MMC related functions if enabledMaxime Ripard2015-10-20-1/+5
| | | | | | | | | | | So far, even if CONFIG_MMC was not enabled the board code was trying to use the MMC-related functions, resulting in linker errors. Protect those calls by an ifdef. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: power: Unify axp pmic function namesHans de Goede2015-10-20-11/+2
| | | | | | | | | Stop prefixing the axp functions for setting voltages, etc. with the model number, there ever is only one pmic driver built into u-boot, this allows simplifying the callers. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Switch to using malloc_simple for the splHans de Goede2015-10-20-0/+1
| | | | | | | | | | common/dlmalloc.c is quite big, both in .text and .data usage. E.g. for a Mele_M9 sun6i board build this reduces .text from 0x4214 to 0x3b94 bytes, and .data from 0x54c to 0x144 bytes. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Tom Rini <trini@konsulko.com>
* armv8/mmu: Set bits marked RES1 in TCRThierry Reding2015-10-15-3/+3
| | | | | | | | | | | For EL3 and EL2, the documentation says that bits 31 and 23 are reserved but should be written as 1. For EL1, only bit 23 is not reserved, so only write bit 31 as 1. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge remote-tracking branch 'u-boot/master'Albert ARIBAUD2015-10-14-882/+2282
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| * ls102xa: Fix reset hangFabio Estevam2015-10-12-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 623d96e89aca6("imx: wdog: correct wcr register settings") issuing a 'reset' command causes the system to hang. Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian. This means that the watchdog on LS1021 has been working by accident as it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c. Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only revelead the endianness problem on LS102x. In order to fix the reset hang, introduce a reset_cpu() implementation that is specific for ls102x, which accesses the watchdog WCR register in big-endian format. All that is required to reset LS102x is to clear the SRS bit. This approach is a temporary workaround to avoid a regression for LS102x in the 2015.10 release. The proper fix is to make the watchdog driver endian-aware, so that it can work for i.MX, Vybrid and LS102x. Reported-by: Sinan Akman <sinan@writeme.com> Tested-by: Sinan Akman <sinan@writeme.com> Reviewed-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * lpc32xx: fix calculation of HCLK PLL output clockVladimir Zapolskiy2015-10-11-5/+5
| | | | | | | | | | | | | | | | Execution branches on feedback mode are swapped, this has no effect if default direct mode is on (then p_div is equal to 1 and Fout equals to Fcco), that's why the problem remained unnoticed for a long time. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
| * arndale: Apply Cortex-A15 errata #773022 and #774769Ian Campbell2015-10-11-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We run 4 Arndale boards in our automated test framework, they have been running quite happily for quite some time using a Debian Wheezy userspace. However when upgrading to a Debian Jessie we started seeing frequent segmentation faults from gcc when building the kernel, to the extent that it is unable to successfully build the kernel twice in a row, and often fails on the first attempt. Searching around I found https://bugs.launchpad.net/arndale/+bug/1081417 which pointed towards http://www.spinics.net/lists/kvm-arm/msg03723.html and CPU Errata 773022 and 774769. This errata needs to be applied to all processors in an SMP system, meaning that the usual strategy of applying them in arch/arm/cpu/armv7/start.S is not appropriate (since that applies to the boot processor only). Instead we apply these errata in the secure monitor which is code that is traversed by all processors as they are brought up. The net affect on Arndale is that ACTLR changes from 0x40 to 0x2000042. I ran 17 kernel compile iterations overnight with no segfaults. Runtime testing was done on our v2014.10 based branch and forward ported (with only minimal and trivial contextual conflicts) to current master, where it has been build tested only. I suppose in theory these errata apply to any Exynos5250 based boards, but Arndale is the only one I have access to and I have therefore chosen to be conservative and only apply it there. Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list numerically sorted. Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
| * Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-10-02-0/+2
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| | * imx: mx6: correct enable_fec_anatop_clockPeng Fan2015-10-02-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock, otherwise we may overridden configuration before enable_fec_anatop_clock. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | sunxi: retrieve FEL-provided values to environment variablesBernhard Nortmann2015-09-29-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends the misc_init_r() function on sunxi boards to test for the presence of a suitable "sunxi" SPL header. If found, and the loader ("fel" utility) provided a non-zero value for the boot.scr address, then the corresponding environment variable fel_scriptaddr gets set. misc_init_r() also sets (or clears) the "fel_booted" variable depending on the active boot device, using the same logic as spl_boot_device(). The goal is to provide sufficient information (within the U-Boot environment) to make intelligent decisions on how to continue the boot process, allowing specific customizations for the "FEL boot" case. Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Simplify spl board_init_f functionHans de Goede2015-09-29-5/+0
| |/ | | | | | | | | | | | | | | crt0.S will both memset the bss sectioan and call board_init_r for us, so there is no need to do either ourselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * imx: fix coding stylePeng Fan2015-09-24-1/+1
| | | | | | | | | | | | | | Fix coding style. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx7: discard unused global variablePeng Fan2015-09-24-2/+0
| | | | | | | | | | | | | | Discard unused global variable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx7: drop select CPU_V7 for board targetPeng Fan2015-09-20-1/+0
| | | | | | | | | | | | | | drop select CPU_V7 for board target, since ARCH_MX7 selects CPU_V7. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * armv8: Make COUNTER_FREQUENCY optionalThierry Reding2015-09-16-0/+2
| | | | | | | | | | | | | | | | | | | | Some platforms have the means to determine the counter frequency at runtime, so give them an opportunity to do so. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * arm: Remove unused ST-Ericsson u8500 archStefan Roese2015-09-15-630/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This arch does not seem to be supported / used at all in the current U-Boot mainline source tree any more. So lets remove the core u8500 code and code that was only referenced by this platform. Please note that this patch also removes these config options: - CONFIG_PL011_SERIAL_RLCR - CONFIG_PL011_SERIAL_FLUSH_ON_INIT As they only seem to be referenced by u8500 based boards. Without any such board in the current code, these config option don't make sense any more. Lets remove them as well. If someone still wants to use this platform, then please send patches to re-enable support by adding at least one board that references this code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: John Rigby <john.rigby@linaro.org> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heiko Schocher <hs@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2015-09-13-1/+7
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| | * arm: rmobile: Add Stout board supportVladimir Barinov2015-08-31-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stout is an entry level development board based on R-Car H2 SoC (R8A7790) This commit supports the following peripherals: - SCIFA, I2C, Ethernet, QSPI, SDHI0/2, CPLD Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | imx: mx6 discard 'select CPU_V7' for different targetsPeng Fan2015-09-13-24/+0
| | | | | | | | | | | | | | | | | | | | | | | | Discard the 'select CPU_V7' from Kconfig in arch/arm/cpu/armv7/mx6 for different targets, because ARCH_MX6 selects CPU_V7. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ul: support mx6ul 9x9 evk boardPeng Fan2015-09-13-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to support mx6ul_9x9_evk board based on mx6ul_14x14_evk, the difference between mx6ul 9x9 evk and mx6ul 14x14 evk are: 1. mx6ul 9x9 evk use pfuze3000, while mx6ul 14x14 evk use DCDC. 2. mx6ul 9x9 evk supports 256MB LPDDR2, while mx6ul 14x14 evk supports 512MB DDR3 3. mx6ul_9x9_evk use 9x9 package, while mx6ul_14x14_evk use 14x14 package. This patch add the following: 1. Discard PHYS_SDRAM_SIZE from header file, use imx_ddr_size() 2. Introduce a macro is_mx6ul_9x9_evk using CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) to avoid "#ifdef xxx" in non-SPL part. To SPL part, CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) can not work, so still use "#ifdef CONFIG_TARGET_MX6UL_9X9_EVK" to differentiate with mx6ul_14x14_evk. And we have no way to dymaically checking this chip is 9x9 or 14x14. 3. mx6ul_9x9_evk use pfuze3000, so enabled POWER related configurations. POWER related configurations also effect for mx6ul_14x14_evk. But power_init_board implementation using 'if (is_mx6ul_9x9_evk())' to do initialization for mx6ul_9x9_evk, and do nothing for mx6ul_14x14_evk. 4. mx6ul_9x9_evk use lpddr2 with size 256MB, so add related SPL DRAM configurations. 5. Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and setting dtb file according to board_rev and board_name. 6. Add TARGET_MX6UL_9X9_EVK Kconfig entry Boot Log: U-Boot SPL 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53) reading u-boot.img reading u-boot.img U-Boot 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53 +0800) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 41C Reset cause: POR Board: MX6UL 9x9 EVK I2C: ready DRAM: 256 MiB PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: FEC1 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * | Revert "imx: mx6: ddr correct tRFC and tXS"Peng Fan2015-09-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 059323fb6a8f21637bb617919715c2427f24777c. This commit 059323fb6a8f21637bb617919715c2427f24777c use JESD79-3E which is not the newest spec. Should use JESD79-3F in which tRFC is 260ns for 4Gb chip. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | imx: mx7dsabresd: Add support for MX7D SABRESD boardAdrian Alonso2015-09-13-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add i.MX7D SABRESD target board support with enabled modules: UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX. Build target: mx7dsabresd_config Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | imx: imx7d: add imx-common cpu support for imx7dAdrian Alonso2015-09-13-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add imx-common cpu support for imx7d SoC - Update reset_cause for imx7d - Enable watchdog driver built for imx7d Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | arm: imx-common: init: rework wdog settings for imx6/imx7Adrian Alonso2015-09-13-14/+0
| | | | | | | | | | | | | | | | | | Rework imx_set_wdog_powerdown to be reused by imx6 and imx7 Signed-off-by: Adrian Alonso <aalonso@freescale.com>
generated by cgit v1.1 at 2024-11-10 04:32:45 +0000