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* ARM64: zynqmp: Add missing SPL dependency for boot.bin generationMichal Simek2016-12-20-0/+1
| | | | | | | boot.bin file is generated only when SPL is selected. Reflect this depency in Kconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: mxs: Remove unused variable warningMarek Vasut2016-12-19-2/+2
| | | | | | | | | | | | | Shuffle the macros around a little to remove the following warning when building for i.MX28: arch/arm/cpu/arm926ejs/mxs/spl_boot.c:44:26: warning: ‘iomux_boot’ defined but not used [-Wunused-const-variable=] static const iomux_cfg_t iomux_boot[] = { ^~~~~~~~~~ Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Stefano Babic <sbabic@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-12-18-32/+182
|\ | | | | | | | | | | Migrate CONFIG_ARCH_USE_MEMSET/MEMCPY with this merge. Signed-off-by: Tom Rini <trini@konsulko.com>
| * imx6: icorem6_rqs: Add FEC supportJagan Teki2016-12-16-0/+1
| | | | | | | | | | | | | | | | | | Add FEC support for Engicam i.CoreM6 RQS modules. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx6: geam6ul: Add FEC supportJagan Teki2016-12-16-0/+1
| | | | | | | | | | | | | | | | | | Add FEC support for Engicam GEAM6UL module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx6: icorem6_rqs: Add I2C supportJagan Teki2016-12-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C support for Engicam i.CoreM6 RQS modules. icorem6qdl-rqs> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 icorem6qdl-rqs> i2c dev 0 Setting bus to 0 icorem6qdl-rqs> i2c speed 100000 Setting bus speed to 100000 Hz icorem6qdl-rqs> i2c probe Valid chip addresses: 4F icorem6qdl-rqs> i2c md 4F 0xff 00ff: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ icorem6qdl-rqs> i2c bus Bus 0: i2c@021a0000 (active 0) 4f: generic_4f, offset len 1, flags 0 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: imx6q: Add Engicam i.CoreM6 Quad/Dual RQS Starter Kit initial supportJagan Teki2016-12-16-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot from MMC: ------------- U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44) Trying to boot from MMC1 U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44 +0530) CPU: Freescale i.MX6D rev1.2 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 Quad/Dual RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl-rqs> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx6: geam6ul: Add I2C supportJagan Teki2016-12-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C support for Engicam GEAM6UL module. geam6ul> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 geam6ul> i2c dev 0 Setting bus to 0 geam6ul> i2c dev Current bus is 0 geam6ul> i2c speed 100000 Setting bus speed to 100000 Hz geam6ul> i2c probe Valid chip addresses: 2C geam6ul> i2c md 2C 0xff 00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00 .......d........ Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: imx6ul: Add Engicam GEAM6UL Starter Kit initial supportJagan Teki2016-12-16-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot Log: -------- U-Boot SPL 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30) Trying to boot from MMC1 U-Boot 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30 +0530) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 43C Reset cause: POR Model: Engicam GEAM6UL DRAM: 128 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 geam6ul> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx6: icorem6: Add I2C supportJagan Teki2016-12-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C support for Engicam i.CoreM6 qdl board. icorem6qdl> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 icorem6qdl> i2c dev 2 Setting bus to 2 icorem6qdl> i2c speed 100000 Setting bus speed to 100000 Hz icorem6qdl> i2c probe Valid chip addresses: 2C icorem6qdl> i2c md 2C 0xff 00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00 .......d........ Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Heiko Schocher <hs@denx.de>
| * icorem6: Use CONFIG_DM_ETH supportJagan Teki2016-12-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_DM_ETH and remove board_eth_init code from board files. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: imx: add i.MX53 Beckhoff CX9020 Embedded PCPatrick Bruenn2016-12-16-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
| * arm: imx: add i.MX6SLL EVK board supportPeng Fan2016-12-16-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX6SLL EVK board support. 1. Add imx6sll-evk device tree. 2. Enable SDHC/I2C/UART. 3. Enable REGULATOR/PMIC/I2C/GPIO/SDHC/PINCTRL driver. Boot Log: U-Boot 2016.11-00127-gc635871-dirty (Nov 24 2016 - 13:28:19 +0800) CPU: Freescale i.MX6SLL rev1.0 at 792MHz CPU: Commercial temperature grade (0C to 95C)Reset cause: POR Model: Freescale i.MX6SLL EVK Board Board: MX6SLL EVK DRAM: 2 GiB i2c bus 0 at 35258368, no gpio pinctrl state. PMIC: PFUZE100! DEV_ID=0x10 REV_ID=0x21 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6sll: add Kconfig entry for i.MX6SLLPeng Fan2016-12-16-0/+4
| | | | | | | | | | | | add Kconfig entry for i.MX6SLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6sll: add clock supportPeng Fan2016-12-16-7/+21
| | | | | | | | | | | | | | Add clock support for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: clock: gate clk before changing pix clk muxPeng Fan2016-12-16-20/+30
| | | | | | | | | | | | | | | | | | | | | | The LCDIF Pixel clock mux is not glitchless, so need to gate before changing mux. Also change enable_lcdif_clock prototype with a new input parameter to indicate disable or enable. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6sl: add lcdif clock supportPeng Fan2016-12-16-19/+59
| | | | | | | | | | | | Add lcdif clock support for i.MX6SL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6: lcdif: gate clock before changing muxPeng Fan2016-12-16-0/+10
| | | | | | | | | | | | | | | | The mux for the lcd clock is not glitchless, so need to first gate the clock before changing the mux. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx6: fix mmdc ch0 clk for 6SLPeng Fan2016-12-16-0/+5
| | | | | | | | | | | | | | | | | | | | >From RM, per_periph2_clk_sel option3 is: "derive clock from 198MHz clock (divided 392MHz PLL2 PFD)." So fix it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * board/liteboard: Add support for liteBoardMarcin Niestroj2016-12-16-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | liteBoard is a development board which uses liteSOM as its base. Hardware specification: * liteSOM (i.MX6UL, DRAM, eMMC) * Ethernet PHY (id 0) * USB host (usb_otg1) * MicroSD slot (uSDHC1) Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
| * udoo_neo: Add thermal supportBreno Lima2016-12-16-0/+2
| | | | | | | | | | | | | | Add thermal support on the Kconfig file. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * udoo_neo: Move MX6SX configuration to KconfigBreno Lima2016-12-16-0/+1
| | | | | | | | | | | | | | | | | | It's not necessary to define the processor in the defconfig file. The preferred method to select the SoC is via Kconfig file. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * arm: imx: initial support for colibri imx6Max Krummenacher2016-12-16-0/+8
| | | | | | | | | | | | | | | | This adds board support for the Toradex module family Colibri iMX6. The familiy consists of a module with i.MX6 DualLite, i.MX6 Solo, both with a version for commercial and industrial temperature range. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| * arm: imx: initial support for apalis imx6Max Krummenacher2016-12-16-0/+8
| | | | | | | | | | | | | | | | This adds board support for the Toradex module family Apalis iMX6. The familiy consists of a module with i.MX6 Dual, i.MX6 Quad with commercial and industrial temperature range. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
* | ARMv8: LS1043A: Enable LS1043A default PSCI supportmacro.wave.z@gmail.com2016-12-15-0/+21
| | | | | | | | | | | | | | | | | | | | A most basic PSCI implementation with only one psci_version is added for LS1043A, this can verify the generic PSCI framework, and more platform specific implementation will be added later. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | ARMv8: Setup PSCI memory and device treemacro.wave.z@gmail.com2016-12-15-1/+32
| | | | | | | | | | | | | | | | | | Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | ARMv8: Add basic PSCI frameworkmacro.wave.z@gmail.com2016-12-15-0/+297
| | | | | | | | | | | | | | | | | | | | This patch introduces a generic ARMv8 PSCI framework, with all functions returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each platform to implement their own functions based on this framework. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | ARMv8: Add secure sections for PSCI text and datamacro.wave.z@gmail.com2016-12-15-0/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to hold PSCI text and data, and it is based on the legacy implementation of ARMv7. ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here in Kconfig too. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definitionmacro.wave.z@gmail.com2016-12-15-5/+27
|/ | | | | | | | | | | | NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: armv7: add us timer for bootstagePatrick Delaunay2016-12-09-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | solve issue when bootstage is used with armV7 generic timer first call of timer_get_boot_us() use the function get_timer() before timer initialization (arch.timer_rate_hz = 0) => div by 0 Commit-notes When I activate bootstage on ARMV7 architecture with platform using the generic armv7 timer defined in file ./arch/arm/cpu/armv7m/timer.c I have a issue because gd->arch.timer_rate_hz = 0 For me the get_timer() function should not used before timer_init (which initialize gd->arch.timer_rate_hz) at least for the ARMV7 timer. But in the init sequence, the first bootstage fucntion is called before timer_init and this function use the timer function. For me it is a error in the generic init sequence : mark_bootstage is called before timer_init. static init_fnc_t init_sequence_f[] = { .... arch_cpu_init_dm, mark_bootstage, /* need timer, go after init dm */ ... #if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \ defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \ defined(CONFIG_SPARC) timer_init, /* initialize timer */ #endif ....... To solve the issue for all the paltform, we can move timer_init() call just before mark_bootstage() in this array... It should be ok for ARMV7 but I don't sure for other platform impacted - the other ARM platform or ARMV7 wich don't use generic timer - MIPS BLACKFIN NDS32 or SPARC and I don't sure of impact for other function called (board_early_init_f for example....) => This patch solve issue only in timer armv7 get_boot_us() can be called everytime without div by 0 issue (gd->arch.timer_rate_hz is not used) END Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
* armv8: QSPI: Add AHB bus 16MB+ size supportYuan Yao2016-12-05-0/+49
| | | | | | | | The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080a: Add serdes1 protocol 0x3b supportPriyanka Jain2016-12-05-0/+1
| | | | | Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl/ddr: Add erratum_a009942_check_cpo and clean related erratumShengzhou Liu2016-12-05-1/+6
| | | | | | | | | | | | | - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://git.denx.de/u-boot-mpc85xxTom Rini2016-12-04-0/+11
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| * armv8: fsl-layerscape: Move SECURE_BOOT to KconfigYork Sun2016-12-02-0/+5
| | | | | | | | | | | | Move from CONFIG_SYS_EXTRA_OPTIONS to Kconfig option. Signed-off-by: York Sun <york.sun@nxp.com>
| * armv7: ls1021a: Move SECURE_BOOT option to KconfigYork Sun2016-12-02-0/+6
| | | | | | | | | | | | Move from CONFIG_SYS_EXTRA_OPTIONS to Kconfig option. Signed-off-by: York Sun <york.sun@nxp.com>
* | ARM64: zynqmp: List secondary software boot modesMichal Simek2016-12-02-0/+12
| | | | | | | | | | | | | | | | Using alternative bootmode field to support automatic secondary boot modes. It is purely software setting where SW modes are using free bootmode combinations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Force certain bootmode for SPLMichal Simek2016-12-02-1/+1
| | | | | | | | | | | | | | | | ZynqMP provides an option to overwrite bootmode setting which can change SPL behavior. For example: boot SPL via JTAG and then SPL loads images from SD. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-11-30-49/+152
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| * imx6: clock: Enable External Memory Interface [EIM] clock (eim_slow_clock)Lukasz Majewski2016-11-30-0/+14
| | | | | | | | | | | | | | | | This patch extends the imx6 clock code to enable or disable the EIM slow clock, which in necessary when one wants to use EIM interface t o read/write from external memory (e.g. NOR). Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
| * mx6sx: Add initial support for Samtec VIN|ING 2000 boardChristoph Fritz2016-11-30-0/+7
| | | | | | | | | | | | | | | | This patch adds initial support for Samtec VIN|ING 2000 board. Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Acked-by: Marek Vasut <marex@denx.de>
| * mx6sx: Add initial support for UDOO Neo BoardBreno Lima2016-11-29-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UDOO Neo Board is a development board from Seco that has three models: - UDOO Neo Basic - UDOO Neo Basic Kick Starter - UDOO Neo Extended - UDOO Neo Full All versions are based on the i.MX6 SoloX processor. For more details about the UDOO Neo board, please refer to: http://www.udoo.org/udoo-neo/ This work is based on a previous commit of Francesco Montefoschi <francesco.monte@gmail.com>: https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed574961844 Only tested on the UDOO Neo Full board. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routinesEric Nelson2016-11-29-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR calibration routines are gated by conditionals for the i.MX6DQ SOCs, but with the use of the sysinfo parameter, these are usable on at least i.MX6SDL and i.MX6SL variants with DDR3. Also, since only the Novena board currently uses the dynamic DDR calibration routines, these routines waste space on other boards using SPL. Add a KConfig entry to allow boards to selectively include the DDR calibration routines. Signed-off-by: Eric Nelson <eric@nelint.com>
| * mx6: ddr: add routine to return DDR calibration dataEric Nelson2016-11-29-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | Add routine mmdc_read_calibration() to return the output of DDR calibration. This can be used for debugging or to aid in construction of static memory configuration. This routine will be used in a subsequent patch set adding a virtual "mx6memcal" board, but could also be useful when gathering statistics during an initial production run. Signed-off-by: Eric Nelson <eric@nelint.com>
| * mx6: ddr: pass mx6_ddr_sysinfo to calibration routinesEric Nelson2016-11-29-42/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR calibration routines have scattered support for bus widths other than 64-bits: -- The mmdc_do_write_level_calibration() routine assumes the presence of PHY1, and -- The mmdc_do_dqs_calibration() routine tries to determine whether one or two DDR PHYs are active by reading MDCTL. Since a caller of these routines must have a valid struct mx6_ddr_sysinfo for use in calling mx6_dram_cfg(), and the bus width is available in the "dsize" field, use this structure to inform the calibration routines which PHYs are active. This allows the use of the DDR calibration routines on CPU variants like i.MX6SL that only have a single MMDC port. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * mx6: ddr: allow 32 cycles for DQS gating calibrationEric Nelson2016-11-29-0/+7
| | | | | | | | | | | | | | | | | | | | | | The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample cycle) for the first PHY. Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0 output value isn't polluted with calibration artifacts. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2016-11-29-15968/+412
| |\ | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: update the REFTOP_VBGADJ settingPeng Fan2016-11-16-5/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to design team, we need to set REFTOP_VBGADJ in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the actually table is as below: '000" - set REFTOP_VBGADJ[2:0] to 3'b000 '001" - set REFTOP_VBGADJ[2:0] to 3'b001 '010" - set REFTOP_VBGADJ[2:0] to 3'b010 '011" - set REFTOP_VBGADJ[2:0] to 3'b011 '100" - set REFTOP_VBGADJ[2:0] to 3'b100 '101" - set REFTOP_VBGADJ[2:0] to 3'b101 '110" - set REFTOP_VBGADJ[2:0] to 3'b110 '111" - set REFTOP_VBGADJ[2:0] to 3'b111 Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
| * | imx: mx6sx: Disable ENET clock before switching clock parentYe.Li2016-11-16-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Need to gate ENET clock when switching to a new clock parent, because the mux is not glitchless. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | | armv7: psci: cpu_off: flush D-Cache before disable D-CachePeng Fan2016-11-29-0/+4
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before disable cache, need to first flush cache. There maybe dirty data in D-Cache before disable D-Cache. After disable D-Cache, the first store instructions in psci_v7_flush_dcache_all will directly store registers {r4-r5, r7, r9-r11, lr} to memory. If there is dirty data before disable D-Cache, psci_v7_flush_dcache_all will flush data to memory, and may overwrite the memory that hold the registers {r4-r5, r7, r9-r11, lr}. So before disable cache, first flush D-Cache. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: York Sun <york.sun@nxp.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Tom Rini <trini@konsulko.com>
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