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* davinci: Do not duplicate setting of gdTom Rini2015-01-29-16/+1
| | | | | | | | | | In f0c3a6c we stopped setting gd in board_init_f, but later had to revert to due problems on certain platforms. As davinci does not look to have these problems, we can drop the setting here and rely upon crt0.S to do it. Cc: Peter Howard <pjh@northern-ridge.com.au> Signed-off-by: Tom Rini <trini@ti.com>
* omap3: make SDRC SHARING setting configurableAlbert ARIBAUD \(3ADEV\)2015-01-29-1/+5
| | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* omap3: enable GP9 timer and UART2Albert ARIBAUD \(3ADEV\)2015-01-29-0/+9
| | | | | | These are needed for the upcoming Cairo board support. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* ARM: OMAP5: DRA7xx: Add support for power rail groupingLubomir Popov2015-01-29-25/+101
| | | | | | | | | | | | | | | | | | | | | | On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC core rails. This concept of using one SMPS to supply multiple core domains (in various, although limited combinations, per primary device use case) has now become common and is used by many customer J6/J6Eco designs; it is supported by a number of corresponding PMIC OTP versions. This patch implements correct operation of the core voltages scaling routine by ensuring that each SMPS that is supplying more than one domain shall be written only once, and with the highest voltage of those fused in the SoC (or of those defined in the corresponding header if fuse read is disabled or fails) for the power rails belonging to the group. The patch also replaces some PMIC-related magic numbers with the appropriate definitions. The default OPP_NOM voltages for the DRA7xx SoCs are updated as well, per the latest DMs. Signed-off-by: Lubomir Popov <l-popov@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-01-26-0/+18
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| * ARM: atmel: sama5d4: add usb device initial codeBo Shen2015-01-19-0/+16
| | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * arm, arm926ejs: make thumb mode compileableHeiko Schocher2015-01-19-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c when enabling CONFIG_SYS_THUMB_BUILD: {standard input}: Assembler messages: {standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0' {standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0' so, if caches are disabled, do not use this command on arm926ejs. used on at91 in SPL, to reduce size of SPL. Signed-off-by: Heiko Schocher <hs@denx.de>
* | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-01-26-5/+46
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| * | ARM: zynq: List nand, qspi and jtag boot modesMichal Simek2015-01-26-0/+9
| | | | | | | | | | | | | | | | | | Use full boot mode list in SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: slcr: Dont modify the reserved bitsSiva Durga Prasad Paladugu2015-01-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set only the 0-3 bits of the FPGA_RST_CTRL register as other bits should not be set to 1. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: ddrc: Setup half of memory only for ECC caseMichal Simek2015-01-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Setup half of memory from ram_size for ECC case. All the time the same board can be configured with or without ECC. Based on ECC case detection use half of memory with the same configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Remove empty lineMichal Simek2015-01-26-1/+0
| | | | | | | | | | | | | | | | | | Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Enable the Neon instructionsMichal Simek2015-01-26-3/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added the lowlevel_init to enable the Neon instructions. Initially the u-boot was causing undefined instruction exception if loaded through tcl, and working fine if loaded through FSBL. The exception was causing in convertion formula of given time to ticks. It was because, the Neon instructions were disabled and hence causing the undefined exception. In FSBL case, the FSBL was enabling the Neon instructions. Hence, added the lowlevel_init to enable the Neon instructions. Also enable neon instructions for non-xilinx toolchain. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-marvellTom Rini2015-01-25-3/+8
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| * | | ARM: kirkwood: fix cpu info for 6282 device idLuka Perkov2015-01-25-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Luka Perkov <luka@openwrt.org> Acked-By: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Stefan Roese <sr@denx.de>
* | | | fsl/ls1021qds: Add deep sleep supporttang yuantian2015-01-24-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add deep sleep support on Freescale LS1021QDS platform. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> [York Sun: Fix conflict in fdt.c] Reviewed-by: York Sun <yorksun@freescale.com>
* | | | ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD bootAlison Wang2015-01-23-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are only enabled in QSPI boot, and disabled in other boot modes. IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot. This patch will add fdt support for the above rules. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | ARM: HYP/non-sec: Make variable gic_dist_addr as a local onetang yuantian2015-01-23-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Defining variable gic_dist_addr as a globe one prevents some functions, which use it, from being used before relocation which is the case in the deep sleep resume process on Freescale SoC platforms. Besides, we can always get the GIC base address by calling get_gicd_base_address() without referring gic_dist_addr. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | crypto/fsl: Add fixup for crypto nodeRuchika Gupta2015-01-23-0/+17
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Era property is added in the crypto node in device tree. Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to drivers/sec/sec.c so that it can be used across arm and powerpc platforms having crypto node. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> [York Sun: Fix commit message indentation] Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-01-23-4/+70
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| * | | sun9i: Add sun9i (A80) clock setup supportHans de Goede2015-01-22-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial sun9i (A80) clock setup support, enough to get the uart + mmc going. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: Drop pll6 setting from clock_init_uartHans de Goede2015-01-22-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the comment says now that we have SPL support this is no longer necessary, as PLL6 is already setup with the exact same parameters by the SPL. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | | ARM: UniPhier: remove non-sense inline directivesMasahiro Yamada2015-01-23-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The inlining is done by GCC when needed, there is no need to do it explicitly. Furthermore, the inline keyword does not force-inline the code, but is only a hint for the compiler. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | ARM: UniPhier: add static to local functionsMasahiro Yamada2015-01-23-15/+15
| | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | ARM: UniPhier: fix IECTRL set code for PH1-Pro4Masahiro Yamada2015-01-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For PH1-Pro4, the bit 6 of the IECTRL must be set. It is the only available bit in this register. There is no effect of the write access to the other bits. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | ARM: UniPhier: describe init_page_table shorterMasahiro Yamada2015-01-23-1069/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The assembly directive ".rept ... .endr" allows us to write the init_page_table much shorter. To make things further simpler, set the text and stack area as Normal Memory, and the other sections as Device attribute. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | ARM: UniPhier: fix comments in SoC Glue init functionMasahiro Yamada2015-01-23-2/+2
|/ / / | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | sunxi: Restore lowlevel_init usageHans de Goede2015-01-21-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2 recent sunxi changes have removed the usage of lowlevel_init by moving some code around and then setting CONFIG_SKIP_LOWLEVEL_INIT. This is problematic for 2 reasons: 1) It does not just stop s_init from being called, it also stops cpu_init_cp15 from getting called, which is undesirable. 2) We want u-boot.bin to be usable standalone, without SPL, some people e.g. use an upstream u-boot.bin together with Allwinner's boot0 loader. So u-boot.bin must (re)initialize the gpios, timer, etc. This commit restores the lowlevel_init / s_init usage, while keeping the changes to no longer use the global-data (gd) struct in the SPL. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | zynq: Remove reference to gdataSimon Glass2015-01-20-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | The global_data pointer (gd) has already been set before board_init_f() is called. We should not assign it again. We should also not use gdata since it is going away. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | sunxi: Drop use of lowlevel_init()Simon Glass2015-01-16-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | This does nothing now, so drop it. We have SPL anyway to do our low-level init. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: Move SPL s_init() code to board_init_f()Simon Glass2015-01-16-32/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current sunxi implementation uses gdata, which is going away. It also sets up DRAM before board_init_f() in SPL. There is really no reason to do much in s_init() since board_init_f() is called immediately afterwards. The only change is that we need our own implementation of board_init_f() which sets up DRAM before the BSS (which is in DRAM) is cleared. The s_init() code runs once for SPL and again for U-Boot proper. We shouldn't need to init the clock/timer/gpio/i2c init twice, so just have it in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | TI ARMv7: Don't use GD before crt0.S has set itTom Rini2015-01-16-30/+11
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this change we set the gd pointer early so that we can store data in it. This becomes problematic for DM changes as well as being odd in general. Re-work the code paths so that we don't need to set the gd pointer so early and instead can rely upon the normal setting of it. In order to do this we do need to move certain calls from s_init into spl_board_init(), mainly preloader_console_init and save_omap_boot_params. Tested on: Beaglebone Black, AM43xx GP EVM, Beagleboard, Beagleboard xM, OMAP5 uEVM, DRA7xx EVM Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2015-01-16-46/+93
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| * | arm: am437x: Enable hardware leveling for EMIFJames Doublesin2015-01-13-46/+93
| |/ | | | | | | | | | | | | | | | | | | | | | | Switch to using hardware leveling for certain parameters on the EMIF rather than using precalculated values. Doing this also means we have a common place now between am437x and am335x for setting emif_sdram_ref_ctrl with a value for the correct delay length. Tested-by: Felipe Balbi <balbi@ti.com> Tested-by: Tom Rini <trini@ti.com> Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* | ARM: armv8: Fix typo in commentaryMichal Simek2015-01-14-1/+1
| | | | | | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Add support for Seagate BlackArmor NAS220Evgeni Dobrev2015-01-14-0/+4
| | | | | | | | | | | | Add support for Seagate BlackArmor NAS220 Signed-off-by: Evgeni Dobrev <evgeni@studio-punkt.com>
* | sunxi: usbc: Add support for usb-vbus0 controller by axp drivebus pinHans de Goede2015-01-14-0/+26
| | | | | | | | | | | | | | | | | | The axp221 / axp223's N_VBUSEN pin can be configured as an output rather then an input, and this is used on some boards to control usb-vbus0, add support for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: usbc: Add support for usb0 to the common usbc codeHans de Goede2015-01-14-8/+25
| | | | | | | | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Move usb-controller init code out of ehci-sunxi.c for reuse for otgHans de Goede2015-01-14-0/+230
| | | | | | | | | | | | | | | | | | | | Most of the usb-controller init code found in ehci-sunxi.c also is necessary to init the otg usb controller, so move it to a common place. While at it also update various #ifdefs / defines for sun8i support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sun7i: Move psci_arch_init close to text_endJan Kiszka2015-01-14-40/+40
| | | | | | | | | | | | | | | | | | "adr rX, text_end" only works if the label is close. Adding further code to the other functions will prevent this. So move the containing function close to label. No functional change. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sun7i: Add support for taking CPUs offline via PSCIJan Kiszka2015-01-14-0/+171
| | | | | | | | | | | | | | | | | | | | | | Based on the original version by Marc Zyngier. It adds a psci_cpu_off implementation for the A20 SoC. The mechanism works by first preparing the calling CPU to go offline (disable and flush cache, disable SMP), then requesting CPU 0 to pull the plug. The request is sent as FIQ on SGI15. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Fix PLL1 running at half speed on sun8iHans de Goede2015-01-14-2/+6
| | | | | | | | | | | | | | | | | | | | PLL1 on sun6i / sun8i also has a p factor which divides the clock by 2^p (to the power p). On sun6i the p factor is ignored, but on sun8i it is used and we were setting it to 1, resulting in the CPU running at 504 MHz instead of 1008 MHz, this commit fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Fix buggy sun6i/sun8i DRAM size detection logicSiarhei Siamashka2015-01-14-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After reboot, reset or even short power off, DRAM typically retains the old stale data for some period of time (for this type of memory, the bits of data are stored in slowly discharging capacitors). The current sun6i/sun8i DRAM size detection logic, which is inherited from the Allwinner code, relies on using a large magic signature with the hope that it is unique enough and unlikely to ever accidentally match this leftover garbage data in RAM. But this approach is inherently unsafe, as can be demonstrated using the following test program: /***** A testcase for reproducing the problem ******/ void main(int argc, char *argv[]) { size_t size, i; uint32_t *buf; /* Allocate the buffer */ if (argc < 2 || !(size = (size_t)atoi(argv[1]) * 1048576) || !(buf = malloc(size))) { printf("Need buffer size in MiB as a cmdline argument\n"); exit(1); } /* Fill it with the Allwinner DRAM "magic" values */ for (i = 0; i < size / 4; i++) buf[i] = 0xaa55aa55 + ((uintptr_t)&buf[i] / 4) % 64; /* Try to reboot */ system("reboot"); /* And wait */ for (;;) {} } /***************************************************/ If this test program is run on the device (giving it a large chunk of memory), then the DRAM size detection logic in u-boot gets confused after reboot and fails to initialize DRAM properly. A better approach is not to rely on luck and abstain from making any assumptions about the properties of the leftover garbage data in RAM. Instead just use a more reliable code for testing whether two different addresses refer to the same memory location. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sun8i: Add dram initialization supportHans de Goede2015-01-14-1/+349
| | | | | | | | | | | | | | | | Based on the register / dram_para headers from the Allwinner u-boot / linux sources + the init sequences from boot0. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Fill memory before comparing it when doing dram init on sun6iHans de Goede2015-01-14-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sun8i boot0 code fills the DRAM with a "random" pattern before comparing it at different offsets to do columns, etc. detection. The sun6i boot0 code does not do it, instead relying on the memory contents being random enough to begin with for the memcmp to properly detect the wrap-around address, iow it is working purely by chance. Since our sun6i dram code was modelled after the boot0 code it contained the same issue. This commit fixes this by filling the memory with a unique, distinct pattern. The new mctl_mem_fill function this introduces is added as an inline helper in dram.h, so that it can be shared with the sun8i dram code. While at it move mctl_mem_matches to dram.h for re-use in sun8i too. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Move await_completion dram helper to dram.hHans de Goede2015-01-14-37/+11
| | | | | | | | | | | | | | | | | | The await_completion helper is already copy pasted between the sun4i and sun6i dram code, and we need it for sun8i too, so lets make it an inline helper in dram.h, rather then adding yet another copy. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sun6i: clock_set_pll5: Calculate k and m rather then hardcoding themHans de Goede2015-01-14-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Our old hardcoded k and m values are based on PLL5 being configured in steps of 48 MHz, which is correct for sun6i where the DRAM PLL runs at twice the DRAM CLK, which is usually configured in 24 MHz step. But on the A23 (sun8i) the PLL5 runs at half the DRAM CLK, so we require 12 MHz steps. This commit adjusts clock_set_pll5 to automatically select the best k and m depending on the requested clk rate. Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sun6i: Add a sigma_delta_enable paramter to clock_set_pll5()Hans de Goede2015-01-14-3/+8
| | | | | | | | | | | | | | | | The sun8i dram code sometimes wants to enable sigma delta mode, add a parameter to allow this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: axp221: Add axp223 supportHans de Goede2015-01-14-1/+1
| | | | | | | | | | | | | | | | | | The axp223 appears to be the same as the axp221, except that it uses the rsb to communicate rather then the p2wi. At least all the registers we use are 100% the same. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Add support for the rsb (Reduced Serial Bus)Hans de Goede2015-01-14-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | sun8i (A23) introduces a new bus for communicating with the pmic, the rsb, the rsb is also used to communicate with the pmic on the A80, and is documented in the A80 user manual. This commit adds support for this based on the rsb driver from the allwinner u-boot sources. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
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