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* arm: rmobile: koelsch: Update to QoS revision 0.411Nobuhiro Iwamatsu2015-06-01-1/+1
| | | | | | | | This updates r8a7791 QoS to revision 0.411. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* arm: rmobile: lager: Update to QoS revision 0.973Nobuhiro Iwamatsu2015-06-01-0/+22
| | | | | | | | | This updates r8a7790 QoS to revision 0.973. This commit can changed from KConfig to fit contents of the QoS. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* ARMv7M: add STM32F1 supportMatt Porter2015-05-28-0/+548
| | | | | | Add ARMv7M STM32F1 support including clocks, timer, gpio, and flash. Signed-off-by: Matt Porter <mporter@konsulko.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-05-26-12/+103
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| * arm, imx6, i2c: add I2C4 for MX6DLHeiko Schocher2015-05-26-11/+22
| | | | | | | | | | | | add I2C4 modul for MX6DL based boards. Signed-off-by: Heiko Schocher <hs@denx.de>
| * imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTPTim Harvey2015-05-19-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480 in the Fusemap Description Table in the reference manual. Return this value as well as min/max temperature based on the value. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. This has been tested with IMX6 Automative and Industrial parts. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: mx6: add get_cpu_speed_grade_hz func to return MHz speed grade from OTPTim Harvey2015-05-19-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description Table. Return this frequency so that it can be used elsewhere. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * arm: mx6: ddr: set fast-exit on DDR3 if pd_fast_exit specifiedTim Harvey2015-05-19-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support to the MMDC however enabling it on the DDR3 got missed. Make sure we enable it on the DDR3 as well. Gateworks uses Micron memory as well as Winbond in MX6. We have found in testing that we need to enable fast-exit for Winbond stability. Gateworks boards are currently the only boards using the MX6 SPL and enabling fast-exit mode. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | sunxi: Make DRAM_ODT_EN Kconfig setting a boolHans de Goede2015-05-19-14/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make DRAM_ODT_EN Kconfig setting a bool, add a separate DRAM_ODT_CORRECTION setting for A23 SoCs and use DRAM_ODT_EN Kconfig everywhere instead of only in dram_sun4i.c and hardcoding odt_en elsewhere. Note this commit makes no functional changes for existing boards, its purpose is to allow changing the odt_en value on future A33 boards. For sun4i/sun5i/sun7i boards which set DRAM_ODT_EN=y (which no defconfigs currently do) this patch turns on odt for both the DQ and the DQS lines, whereas previously it was possibly (but not desirable) to turn odt on only for one of them by setting the in DRAM_ODT_EN option to 1 or 2 instead of 3. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
* | sunxi: Fix dram initialization not working on some a33 devicesHans de Goede2015-05-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | When porting the allwinner dram init code to u-boot we missed some code setting an extra bit when doing auto dram config. This commits add this bit, fixing dram init not working on the ga10h 10" a33 tablet which I'm bringing up atm. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: add support for UART2 on A23/A33Laurent Itti2015-05-19-0/+4
| | | | | | | | | | | | | | | | | | | | Add support for UART2 (2-pin version but note that RTS/CTS pins are available pn that port for possible future use), can be selected in config by using CONFIG_CONS_INDEX=3 Signed-off-by: Laurent Itti <laurentitti@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge git://git.denx.de/u-boot-samsungTom Rini2015-05-18-28/+37
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| * exynos: clock: clean up checkpatch issuesMinkyu Kang2015-05-18-28/+37
| | | | | | | | Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | arm: mx6: ddr3: Remove dead codeNikolay Dimitrov2015-05-15-22/+0
| | | | | | | | | | | | | | imx6 mmdc supports data rates up to 1066 MT/s, so remove the code handling higher data rates. Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
* | mx6: Set shared override bit in PL310 AUX_CTRL registerFabio Estevam2015-05-15-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having bit 22 cleared in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. This was inspired by a patch from Catalin Marinas [1] and also from recent discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring suggested that bootloaders should initialize the cache. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html [2] https://lkml.org/lkml/2015/2/20/199 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
* | arm: mx6: Clamp MMDC and DDR3 clocks for timing calculationsNikolay Dimitrov2015-05-15-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported frequencies as per imx6 SOC models, and for dynamically calculating valid clock value based on mem_speed. Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which doesn't take into account DDR3 memory limitations. Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com>
* | tegra: Boot in non-secure mode by defaultJan Kiszka2015-05-13-1/+1
| | | | | | | | | | | | | | | | | | | | Upstream Linux is broken with default configs when PSCI, thus non-secure mode is enabled. So the user should explicitly enable this mode, e.g. when she disabled CONFIG_CPU_IDLE in Linux (in which case it's safe to use). We can revert this workaround once Linux got fixed. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0Ian Campbell2015-05-13-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: Add board-specific initialization hook for PSCIJan Kiszka2015-05-13-0/+6
| | | | | | | | | | | | | | | | Tegra boards will have to initialize power management for the PSCI support this way. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | virt-dt: Allow reservation of secure region when in a RAM carveoutJan Kiszka2015-05-13-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In this case the secure code lives in RAM, and hence the memory node in the device tree needs to be adjusted. This avoids that the OS will map and possibly access the reservation. Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out such a region. We only support cutting off memory from the beginning or the end of a RAM bank as we do not want to increase their number (which would happen if punching a hole) for simplicity reasons This will be used in a subsequent patch for Jetson-TK1. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: Put target PC for PSCI CPU_ON on per-CPU stackJan Kiszka2015-05-13-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a per-CPU variable for saving the target PC during CPU_ON operations. This allows us to run this service independently on targets that have more than 2 cores and also core-local power control. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: Factor out reusable psci_get_cpu_stack_topJan Kiszka2015-05-13-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | This algorithm will be useful on Tegra as well, plus we will need it for making _psci_target_pc per-CPU. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: Factor out reusable psci_cpu_entryJan Kiszka2015-05-13-18/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | _sunxi_cpu_entry can be converted completely into a reusable psci_cpu_entry. Tegra124 will use it as well. As with psci_disable_smp, also the enabling is designed to be overloaded in cased SMP is not controlled via ACTLR. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: Factor out reusable psci_cpu_off_commonJan Kiszka2015-05-13-62/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely cache disabling and flushing, clrex and the disabling of SMP for the dying CPU. These steps are apparently generic for ARMv7 and will be reused for Tegra124 support. As the way of disabled SMP is not architectural, though commonly done via ACLTR, the related function can be overloaded. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: Factor out common psci_get_cpu_idJan Kiszka2015-05-13-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Will be required for obtaining the ID of the current CPU in shared PSCI functions. The default implementation requires a dense ID space and only supports a single cluster. Therefore, the functions can be overloaded in cases where these assumptions do not hold. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditionsJan Kiszka2015-05-13-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those. CC: Tang Yuantian <Yuantian.Tang@freescale.com> CC: York Sun <yorksun@freescale.com> CC: Steve Rae <srae@broadcom.com> CC: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | arch: Make board selection choices optionalJoe Hershberger2015-05-12-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | By making the board selections optional, every defconfig will include the board selection when running savedefconfig so if a new board is added to the top of the list of choices the former top's defconfig will still be correct. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com>
* | ARM: socfpga: abolish CONFIG_SOCFPGAMasahiro Yamada2015-05-07-1/+1
| | | | | | | | | | | | Replace CONFIG_SOCFPGA with CONFIG_ARCH_SOCFPGA. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: socfpga: move SoC sources to mach-socfpgaMasahiro Yamada2015-05-07-1876/+0
| | | | | | | | | | | | Our recent trend is to collect SoC files into arch/arm/mach-(SOC). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: socfpga: remove redundant config.mkMasahiro Yamada2015-05-07-8/+0
| | | | | | | | | | | | | | | | Because all the SOCFPGA boards define CONFIG_SPL_FRAMEWORK (see include/configs/socfpga_common.h), u-boot.img is automatically added to the target image list by the top Makefile. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: socfpga: do not add board directory to header search pathMasahiro Yamada2015-05-07-3/+0
|/ | | | | | | | | The compiler option "-Iboard/$(VENDOR)/$(BOARD)" just exists here for iocsr_config.c to be able to include iocsr_config.h. Use "..." instead of <...> to include a header in the same directory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge git://git.denx.de/u-boot-marvellTom Rini2015-05-05-302/+0
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| * arm: armada-xp: Move SoC sources to mach-mvebuStefan Roese2015-05-05-302/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move arch/arm/cpu/armv7armada-xp/* -> arch/arm/mach-mvebu/* Since this platform will be extended to support other Marvell SoC's as well, lets rename it directly to mvebu. This will be used by the upcoming Armada 38x suport (A38x). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com> Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-05-05-7/+7
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| * \ Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-05-05-1664/+2000
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| * | ARM: cpu: Add ARMv7 barrier operations supportValentine Barshak2015-04-16-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables ARMv7 barrier operations support when march=armv7-a is enabled. Using CP15 barriers causes U-Boot bootm command crash when transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU. Using ARMv7 barrier operations instead of the deprecated CP15 barriers helps to avoid these issues. Signed-off-by: Valentine Barshak <valentine.barshak+renesas@cogentembedded.com> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* | | sunxi: usb: Protect phy-init and phy-power-on against multiple callsHans de Goede2015-05-04-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Once we add support for the ohci controller the phy-init and phy-power-on functions may be called twice (once by the ehci code and once by the ohci code) protect them against this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: usb: Do not call phy_probe from hcd codeHans de Goede2015-05-04-49/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 2/3 usb-phys on the sunxi SoCs are really a single separate functional block, and are modelled as such in devicetree. So once we've moved all the sunxi usb code to the driver-model then phy_probe will be called once for the entire block from the driver-model enumeration code. Move to this now as this also avoids problems with phy_probe being called multiple times once we introduce ohci support. This also allows us to get rid of the sunxi_usb_phy_enabled_count variable as phy_probe now is guaranteed to be called only once. Since we're effectively rewriting the probe / remove functions, move them to the end of the file while we are at it, as that is the most logical place for them. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: usb: Rename the usbc.? files to usb_phy.?Hans de Goede2015-05-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The usbc.? files now only contain usb-phy related code, rename them to make this clear. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: usb: Rename sunxi_usbc_foo functions to sunxi_usb_phy_barHans de Goede2015-05-04-63/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename the sunxi_usbc_foo functions to sunxi_usb_phy_bar to make it clear that these are usb-phy functions. Also change the verbs & nouns in the suffix to match the verbs & nouns used in the Linux kernels generic phy framework. This patch purely renames things, it contains no functional changes. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: usb: Remove sunxi_usbc_get_io_base functionHans de Goede2015-05-04-20/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the only function left in sunxi/usbc.c which is not phy related, so remove it. This is a preparation patch for turning the usbc.c code into a proper usb phy driver. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: usb: Move setup of host controller clocks to the host controller driversHans de Goede2015-05-04-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sunxi "usbc" code is mostly about phy setup, but currently also sets up the host controller clocks, which is something which really belongs in the host controller drivers, so move it there. This is a preparation patch for moving the sunxi ehci code to the driver model and for adding ohci support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: emac: Remove non driver-model codeHans de Goede2015-05-04-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | All sunxi boards now use the driver-model, so remove the non driver-model code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: emac: Add driver model supportHans de Goede2015-05-04-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Modify the sunxi-emac eth driver to support driver model. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Stefan Roese <sr@denx.de>
* | | sunxi: axp: Add support for i2c based PMICs to the pmic-bus helpersHans de Goede2015-05-04-8/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the axp152 and axp209 PMICs to the pmic register access helpers. This is a preparation patch for moving the axp gpio code to a separate gpio driver. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: axp: Move axp pmic register helpers to a separate fileHans de Goede2015-05-04-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the register helpers used to access the registers via p2wi resp. rsb bus on the otherwise identical axp221 and axp223 pmics to a separate file, so that they can be used by the upcoming standalone axp gpio driver too. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: usbc: Fix vbus gpio handling to work with the driver-modelHans de Goede2015-05-04-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | The driver-model gpio functions may return another value then -1 as error, make the sunxi usbc properly handle this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: Add basic A33 basic supportVishnu Patekar2015-05-04-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Enable full support for the A33 SoC including display, otg-usb, etc. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: Add a33 dram init codeVishnu Patekar2015-05-04-0/+363
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on Allwinner dram init code from the a33 bsp: https://github.com/allwinner-zh/bootloader/blob/master/basic_loader/bsp/bsp_for_a33/init_dram/mctl_hal.c Initial u-boot port by Vishnu Patekar, major cleanup / rewrite by Hans de Goede. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: Add support for A33 PLL11 (second DRAM pll)Hans de Goede2015-05-04-0/+18
| | | | | | | | | | | | | | | | | | | | | Add support for the new second DRAM PLL found on the A33 SoC. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
generated by cgit v1.1 at 2024-08-22 02:14:44 +0000