summaryrefslogtreecommitdiff
path: root/arch/arm/cpu
Commit message (Collapse)AuthorAgeLines
* atmel: at91sam9x5: fix name error for spiBo Shen2012-09-01-2/+2
| | | | | | | Fix the name error Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* mxs: Convert timeout parameter to 'unsigned int'fabio.estevam@freescale.com2012-09-01-2/+4
| | | | | | | | | For representing a timeout value, it makes more sense to pass it as 'unsigned int'. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* gpio: add gpio api support to mx27 (v4)trem2012-09-01-5/+6
| | | | | | | The gpio api has been tested on an armadeus apf27. Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr> Acked-by: Stefano Babic <sbabic@denx.de>
* mxs: Rename 'mx28_dram_init' to 'mxs_dram_init'Otavio Salvador2012-09-01-2/+2
| | | | | | | | | | | | | | | | The DRAM initialization, after SPL has complete, is exactly the same for all mxs SoCs so we should name it accordinly. The following boards has been changed: * apx4devkit * m28evk * mx28evk * sc_sps_1 Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
* mxs: Only build internal Ethernet controller for i.MX28Otavio Salvador2012-09-01-1/+1
| | | | | | | | | The internal Ethernet controller is only available on i.MX28 processors so it needs to use CONFIG_MX28 guardian to avoid having this code called in others. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Marek Vasut <marex@denx.de>
* mx35: Move clock enums to clock.hBenoît Thébaudeau2012-09-01-2/+2
| | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mx35 iomux: Remove unused macroBenoît Thébaudeau2012-09-01-2/+0
| | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* MX28: config: Allow different target generation in elftosb callOtavio Salvador2012-09-01-0/+0
| | | | | | | | The elftosb call needs to use a target param specific for i.MX28. This patch allow for later addition of i.MX233. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Marek Vasut <marex@denx.de>
* mx35: Add cpu_mmc_init()Benoît Thébaudeau2012-09-01-1/+14
| | | | | | | | Add cpu_mmc_init() function to make it easy to init a single eSDHC instance. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mx5/6: Fix cpu_mmc_init() return valueBenoît Thébaudeau2012-09-01-4/+2
| | | | | | | | | Do not pretend to have initialized mmc successfully if CONFIG_FSL_ESDHC is not defined. Instead, only implement a custom cpu_mmc_init() when it does something. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* imx-common/cmd_bmode.c: add imx bmode (bootmode) commandTroy Kisky2012-09-01-0/+187
| | | | | | | | | | | | This is useful for forcing the ROM's usb downloader to activate upon a watchdog reset. Or, you can boot from either SD Card. Currently, support added for MX53 and MX6Q Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Note: MX53 support untested. Acked-by: Stefano Babic <sbabic@denx.de>
* mx5: cosmetic: Clean up lowlevel_initBenoît Thébaudeau2012-09-01-23/+23
| | | | | | | | | | Coding style cleanup: - Remove useless parentheses. - Use tabs for indentations and alignments. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mx5/6 timer: Round up tick_to_time() valueBenoît Thébaudeau2012-09-01-1/+1
| | | | | | | | | | Round up tick_to_time() value instead of truncating it. This avoids stopping waits instantly for low usec values, and this generally guarantees that the code always waits for at least the requested duration. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mx5: Enable dcacheBenoît Thébaudeau2012-09-01-0/+8
| | | | | | | | | Now that the main i.MX features work fine with dcache enabled, enabled it by default if CONFIG_SYS_DCACHE_OFF is not defined. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mx25: Enable dcacheBenoît Thébaudeau2012-09-01-0/+8
| | | | | | | | | Now that the main i.MX features work fine with dcache enabled, enabled it by default if CONFIG_SYS_DCACHE_OFF is not defined. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* MX28: Shuffle around the power management codeMarek Vasut2012-09-01-6/+3
| | | | | | | | | | Move some function calls to a more appropriate place, so they're called only when needed. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* MX28: Drop the cp15 reconfiguration from SPLMarek Vasut2012-09-01-42/+0
| | | | | | | | | | | | | | | The SPL doesn't need the CP15 reconfiguration, as that's what the BootROM does for us already. Moreover, when the CP15 is reconfigured and the code returns control to BootROM, the USB boot works no more. Remove the code and allow [1] to work properly as well. [1] http://git.bfuser.eu/?p=marex/mxsldr.git;a=summary Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mxs: Convert sys_proto.h prefixes to 'mxs'Otavio Salvador2012-09-01-20/+20
| | | | | | | The sys_proto.h functions (except the boot modes) are compatible with i.MX233 and i.MX28 so we use 'mxs' prefix for its methods. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: Remove not required include of iomux-mx28.hOtavio Salvador2012-09-01-1/+0
| | | | | | | The iomux-mx28.h include is not required on spl_mem_init.c so it has been droped. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: Remove not required explicit iomux-mx28.h includeOtavio Salvador2012-09-01-1/+0
| | | | | | | | The iomux header is included on sys_proto.h so to avoid SoC specific header inclusion. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Marek Vasut <marex@denx.de>
* arm:exynos: Enable data cache at exynos based processors.Łukasz Majewski2012-09-01-0/+8
| | | | | | | | | This patch enables the L1 data cache for systems based on Samsung Exynos processor. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: support display port phy control functionDonghwa Lee2012-09-01-0/+21
| | | | | | | | This patch support display port phy control function. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: support display system register controlDonghwa Lee2012-09-01-0/+18
| | | | | | | | This patch supports display block system regisger control. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: support exynos5 lcd clock controlDonghwa Lee2012-09-01-1/+107
| | | | | | | | This patch support exynos5 lcd clock control. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: EXYNOS: fixed compiler warning messageJaehoon Chung2012-09-01-1/+4
| | | | | | | | | | | Removed [-Wuninitialized] warning message. The fout_sel is assigned to "-1" by default. And start, gpio_func is initialized to 0. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm/s5pxx: Fix get_timer_masked to get the time.Zhong Hongbo2012-09-01-5/+17
| | | | | | | | | | | In general, The get_timer_masked function get the system time, no the number of ticks. Such as the nand_wait_ready will use get_timer_masked to delay the operations. And change the system time to adopt to the CONFIG_SYS_HZ. Signed-off-by: Hongbo Zhong <bocui107@gmail.com> Tested-by: Jaehoon Chung<jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-9/+13
| | | | | | | | | | This patch modifies the pinmux settings of MMC and UART as per Exynos5250 Rev 1.0. It also corrects the gpio offset calculations. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: CLOCK: Add BPLL supportRajeshwari Shinde2012-09-01-7/+21
| | | | | | | | This patch adds support for BPLL clock. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-1/+11
| | | | | | | | | | | MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0Tetsuyuki Kobayashi2012-09-01-7/+14
| | | | | | | | | save_boot_params_default() in cpu.c accesses uninitialized stack area when it compiled with -O0 (not optimized). This patch removes save_boot_params_default() and put the equivalent in start.S Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Tom Rini <trini@ti.com>
* tegra20: Remove armv4t build flagsAllen Martin2012-09-01-14/+0
| | | | | | | | | | | These flags were necessary when building tegra20 as a single binary that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support is split into a separate SPL, this is no longer necessary. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: enable SPL for tegra20 boardsAllen Martin2012-09-01-280/+5
| | | | | | | | | | | Add SPL options to tegra20 config files and enable SPL build for tegra20 boards. Also remove redundant code from u-boot that is not contained in SPL. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: move SDRAM param save to later in bootAllen Martin2012-09-01-5/+0
| | | | | | | | | | | | Move warmboot_save_sdram_params() to later in the boot sequence. This code relies on devicetree to get the address of the memory controller and with upcoming changes for SPL boot it gets called early in the boot process when devicetree is not initialized yet. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: add tegra20 support to arm720tAllen Martin2012-09-01-1/+608
| | | | | | | | | | | | | Add support for tegra20 arm7 boot processor. This processor is used to power on the Cortex A9 and transfer control to it. In tegra this processor is an ARM7TDMI not an ARM720T, but since we don't use cache it was easier to just reuse the ARM720T code as the processors are otherwise identical except for cache and MMU. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Fix arm720t SPL buildAllen Martin2012-09-01-0/+13
| | | | | | | | | | | | Take a few SPL fixes from armv7 and apply them to arm720t: -Use dummy exception handlers for SPL build -Initialize relocation register r9 to 0 for the case of no relocation -ifdef out interrupt handler code Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-commonAllen Martin2012-09-01-13/+59
| | | | | | | | | | | In preparation for splitting out the armv4t code from tegra20, move the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will be compiled armv4t for the arm7tdmi and armv7 for the cortex A9. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: rename tegra2 -> tegra20Allen Martin2012-09-01-55/+55
| | | | | | | | | | This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: add basic support for the Broadcom BCM2835 SoCStephen Warren2012-09-01-0/+165
| | | | | | | | | | | | | | | | | This SoC is used in the Raspberry Pi, for example. For more details, see: http://www.broadcom.com/products/BCM2835 http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf. Initial support is enough to boot to a serial console, execute a minimal set of U-Boot commands, download data over a serial port, and boot a Linux kernel. No storage or network drivers are implemented. GPIO driver originally by Vikram Narayanan <vikram186@gmail.com> with many fixes from myself. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* ARM: arm1176: enable instruction cache in arch_cpu_init()Stephen Warren2012-09-01-0/+7
| | | | | | | | | Note that this affects all users of the ARM1176 CPU that enable CONFIG_ARCH_CPU_INIT, not just the BCM2835 SoC, potentially such as tnetv107x. Cc: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* snowball: Adding board specific cache cleanup routineMathieu J. Poirier2012-09-01-0/+26
| | | | | | | | Following ARM's reference manuel for initializing the cache - the kernel won't boot otherwise. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* armv7: Adding cpu specific cache managmenentMathieu J. Poirier2012-09-01-0/+8
| | | | | | | | Some CPU (i.e u8500) need more cache management before launching the Linux kernel. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* u8500: Enabling power to MMC device on AB8500 V2Mathieu J. Poirier2012-09-01-26/+69
| | | | | | | | | Register mapping has changed on power control chip between the first and second revision. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
* u8500: Moving processor-specific functions to cpu area.Mathieu J. Poirier2012-09-01-0/+80
| | | | | | | | | | Functions such as providing power to the MMC device and reading the processor version register should be in the cpu area for access by multiple u8500-based boards. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
* snowball: Moving to ux500.v2 addess scheme for PRCMU accessMathieu J. Poirier2012-09-01-28/+63
| | | | | | | | Addresses between ux500.v1 and ux500.v2 have changed slightly, hence mandating a review of the PRCMU access methods. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* snowball: Adding CPU clock initialisationMathieu J. Poirier2012-09-01-0/+36
| | | | | Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* snowball: Adding architecture dependent initialisationMathieu J. Poirier2012-09-01-1/+72
| | | | | | | Enabling timers and clocks in PRCMU and cleaning up mailbox. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* u8500: Moving prcmu to cpu directoryMathieu J. Poirier2012-09-01-1/+165
| | | | | | | | This is to allow the prcmu functions to be used by multiple u8500-based processors. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* davinci, c6x: Always use C version of reset codeTom Rini2012-09-01-84/+34
| | | | | | | | | We can safely use the same reset code written in C for both Davinci and C6X platforms. In addition the C version of the code is marginally smaller on Davinci. Tested-by: Matt Porter <mporter@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* am33xx evm: Update secure_emif_sdram_config during ddr initSatyanarayana, Sandhya2012-09-01-1/+4
| | | | | | | | | | | | | | | This patch updates secure_emif_sdram_config with the same value written to sdram_config during ddr3 initialization. During suspend/resume, this value is copied into sdram_config. With this, a write to sdram_config at the end of resume sequence which triggers an init sequence can be avoided. Without this register write in place, the DDR_RESET line goes low for a few cycles during resume which is a violation of the JEDEC spec. Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
* da8xx/hawkboard: Add support for ohci host controllerSughosh Ganu2012-09-01-0/+5
| | | | | | | | | | Also enable the ohci port on hawkboard. These additions result in an increased u-boot size -- adjust the same accordingly in the board's config. Move the usb header for da8xx platforms under arch-davinci. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
generated by cgit v1.1 at 2024-08-27 04:37:37 +0000