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* davinci_emac: move arch-independent defines to separate headerIlya Yanok2011-12-06-0/+4
| | | | | | | | | | | DaVinci EMAC is found not only on DaVinci SoCs but on some OMAP3 SoCs also. This patch moves common defines from arch-davinci/emac_defs.h to drivers/net/davinci_emac.h DaVinci specific PHY drivers hacked to include the new header. We might want to switch to phylib in future. Signed-off-by: Ilya Yanok <yanok@emcraft.com>
* omap4: fix IO settingAneesh V2011-12-06-1/+6
| | | | | | | | | | | | The value from TRIM is not working for some 4430 silicons. So, override with hw team recommended value. However, for 4460 TRIM value shall be used as long as the part is trimmed This fixes boot problem on some OMAP4430 ES2.0 Panda boards out there. Cc: Steve Sakoman <sakoman@gmail.com> Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4460: add ES1.1 identificationAneesh V2011-12-06-1/+9
| | | | Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4: emif: fix error in driverAneesh V2011-12-06-2/+2
| | | | | | | | | | There was a typo in the EMIF driver. It went un-noticed because it affected only when automatic detection is enabled and even then half the memory was configured and identified properly. Reported-by: Rockefeller <rockefeller.lin@innocomm.com> Signed-off-by: Aneesh V <aneesh@ti.com>
* omap: remove I2C from SPLAneesh V2011-12-06-1/+0
| | | | | | | Due to some recent changes I2C is no longer required in SPL. Remove the i2c_init() call to save some space Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4460: fix TPS initializationAneesh V2011-12-06-8/+0
| | | | | | | | | | | TPS power IC is controlled using a GPIO (gpio_wk7). This GPIO should be maintained at logic 1 always. As such an internal pull-up on this pin will do the job, driving the GPIO outuput is not needed. This will avoid the need of using GPIO library in SPL and also may save some power. Signed-off-by: Aneesh V <aneesh@ti.com>
* start.S: remove omap3 specific code from start.SAneesh V2011-12-06-23/+8
| | | | | | | Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com> Acked-by: Tom Rini <trini@ti.com>
* armv7: setup vectorAneesh V2011-12-06-0/+17
| | | | | | | | The vector is not correctly setup in armv7 except for OMAP3. Correcting this. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: include armv7/cpu.c in SPL buildAneesh V2011-12-06-2/+2
| | | | | | | | | This allows SPL to have default implementation of save_boot_params(), useful for SoCs that do not intend to override this default implementation Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: disable L2 cache in cleanup_before_linux()Aneesh V2011-12-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | We were not disabling external caches before jumping to kernel. We were flushing all caches including external caches and disabling caches globally in CP15 System Control register. Apparently this is not enough. The bootstrap loader in Linux kernel that does decompression enables data-caches again, flush them after use and disable them before jumping to kernel proper. However, it's not aware of the external caches. Since we have left external cache enabled, external cache will get used once caches are enabled globally, but it's not flushed because decompressor is not aware of external caches. When it jumps to kernel with caches disabled globally, we have stale data in the external cache and a coherency problem. This was breaking the boot for OMAP4 with latest mainline kernel. The solution is to disable external caches in cleanup_before_linux(). With this fix kernel is booting again. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com>
* arm, arm926ejs: Fix clear bss loop for zero length bssChristian Riesch2011-12-06-3/+5
| | | | | | | | This patch fixes the clear bss loop for bss sections that have zero length, i.e., where __bss_start == __bss_end__. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* PXA: Rename pxa_dram_init to pxa2xx_dram_initMarek Vasut2011-12-06-2/+2
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* PXA: Replace timer driverMarek Vasut2011-12-06-52/+35
| | | | | | This new timer driver shall conform to new Timer API. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* PXA: Add cpuinfo display for PXA2xxMarek Vasut2011-12-06-0/+134
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* PXA: Separate PXA2xx CPU initMarek Vasut2011-12-06-73/+31
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* PXA: Rename CONFIG_PXA2[57]X to CONFIG_CPU_PXA2[57]XMarek Vasut2011-12-06-20/+20
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* PXA: Re-add the Dcache locking as RAM for pxa250Marek Vasut2011-12-06-2/+116
| | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefan Herbrechtsmeier <sherbrec@cit-ec.uni-bielefeld.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* PXA: Rework start.S to be closer to other ARMsMarek Vasut2011-12-06-247/+153
| | | | | | | | | | The start.S on PXA was very obscure. This reworks it back to be close to arm1136 start.S and others. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> V2: Don't compile in relocation support if building SPL
* OMAP3: Use sdelay from arch/arm/cpu/armv7/syslib.c instead of cloning that.Alexander Holler2011-11-29-11/+1
| | | | | | | | There is no need to have such a function twice. Signed-off-by: Alexander Holler <holler@ahsoftware.de> Acked-by: Dirk Behme <dirk.behme@googlemail.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* Fix Stelian's email addressStelian Pop2011-11-29-11/+11
| | | | | | | Change my old email address which is no longer valid. Signed-off-by: Stelian Pop <stelian@popies.net> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* Merge branch 'hs@denx.de' of git://git.denx.de/u-boot-stagingWolfgang Denk2011-11-23-2/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'hs@denx.de' of git://git.denx.de/u-boot-staging: drivers/net/dnet.c: Fix GCC 4.6 warnings board/xaeniax/flash.c: Fix GCC 4.6 warnings net/bootp.c: Fix GCC 4.6 warning common/cmd_bootm.c: Fix GCC 4.6 warnings board/mx1ads/mx1ads.c: Fix GCC 4.6 warning board/mx1ads/syncflash.c: Fix GCC 4.6 warnings board/lubbock/flash.c: Fix GCC 4.6 warnings drivers/net/cs8900.c: Fix GCC 4.6 warning arch/arm/cpu/arm926ejs/omap/cpuinfo.c: Fix GCC 4.6 warnings drivers/net/lan91c96.c: Fix GCC 4.6 warning board/ronetix/pm9263/pm9263.c: Fix GCC 4.6 warning drivers/mtd/onenand/samsung.c: Fix GCC 4.6 warning drivers/usb/musb/musb_hcd.c: Fix GCC 4.6 warning
| * arch/arm/cpu/arm926ejs/omap/cpuinfo.c: Fix GCC 4.6 warningsAnatolij Gustschin2011-11-23-2/+3
| | | | | | | | | | | | | | | | | | | | | | Fix: cpuinfo.c: In function 'print_cpuinfo': cpuinfo.c:155:6: warning: variable 'system_serial_low' set but not used [-Wunused-but-set-variable] cpuinfo.c:154:6: warning: variable 'system_serial_high' set but not used [-Wunused-but-set-variable] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | arch/arm/cpu/armv7/s5p-common/pwm.c: fix GCC 4.6 warningAnatolij Gustschin2011-11-16-2/+0
| | | | | | | | | | | | | | | | | | Fix: pwm.c: In function 'pwm_config': pwm.c:85:16: warning: variable 'timer_rate_hz' set but not used [-Wunused-but-set-variable] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | arm, davinci: da850/dm365 lowlevel cleanupHeiko Schocher2011-11-15-124/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Cleanup a lot of fix values, and use defines instead. - Also make some values configurable through the board config file. - delete the NAND_SPL code for da850, as it is not used actually - remove the asm code Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Wolfgang Denk <hs@denx.de> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Tom Rini <tom.rini@gmail.com> Cc: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | omap4/5: Add support for booting with CH.Sricharan2011-11-15-41/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configuration header(CH) is 512 byte header attached to an OMAP boot image that will help ROM code to initialize clocks, SDRAM etc and copy U-Boot directly into SDRAM. CH can help us in by-passing SPL and directly boot U-boot, hence it's an alternative for SPL. However, we intend to support both CH and SPL for OMAP4/5. Initialization done through CH is limited and is not equivalent to that done by SPL. So U-Boot has to distinguish between the two cases and handle them accordingly. This patch takes care of doing this. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | omap5: emif: Add emif/ddr configurations required for omap5 evmSricharan2011-11-15-213/+514
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the emif configurations required for omap5 soc.Add the correct ddr part configurations required for omap5 evm board. EDB8164B3PH from ELPIDA is the part used on the board. Also changes are done to retain some part of the code common for OMAP4/5 and keep only the remaining in the Soc specific directories. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | omap5: clocks: Add clocks support for omap5 platform.Sricharan2011-11-15-470/+991
| | | | | | | | | | | | | | | | | | | | | | | | Adding the correct configurations required for dplls, clocks, for omap5 Soc. Also changes are done to retain some part of the code common for OMAP4/5 and move only the remaining to the Soc specific directories. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | omap5: Add minimal support for omap5430.Sricharan2011-11-15-319/+362
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the minimal support for OMAP5. The platform and machine specific headers and sources updated for OMAP5430. OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Also moved some part of code from the basic platform support that can be made common for OMAP4/5. Rest is kept out seperately. The same approach is followed for clocks and emif support in the subsequent patches. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | omap4: make omap4 code common for future reuseSricharan2011-11-15-9/+16
| | | | | | | | | | | | | | | | | | Much of omap4 soc support code can be reused for omap5. Move them to the omap-common directory to facilitate this. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | mx31: Fix checkpatch warnings in generic.cFabio Estevam2011-11-11-2/+2
| | | | | | | | | | | | | | Fix checkpatch warnings in generic.c. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | mx31: Use proper IO accessor for GPR registerFabio Estevam2011-11-11-2/+3
| | | | | | | | | | | | | | Use proper IO accessor for GPR register. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | mx31: Remove duplicate definition for GPR registerFabio Estevam2011-11-11-4/+2
| | | | | | | | | | | | | | GPR register definition is already available at imx-regs.h, so remove the duplication. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | iMX28: Fix ARM vector handlingMarek Vasut2011-11-11-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces proper ARM vector handling for i.MX28 CPU. This issue wasn't addressed because the interrupts weren't enabled on any ARMv5 core, therefore the issue wasn't noticed earlier. In previous implementation, the vectoring code used by i.MX28 CPU when an exception happened was that of the SPL. With this change, the branch target when an exception happens can be reconfigured by U-Boot. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | iMX28: Add GPIO controlMarek Vasut2011-11-11-0/+6
| | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | iMX28: Add PINMUX controlMarek Vasut2011-11-11-1/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Taken from Linux kernel with minor modifications: commit bf985969e27b507f734435a99df8bf745a3dbb2b Author: Shawn Guo <shawn.guo@freescale.com> Date: Mon Dec 20 22:57:43 2010 +0800 ARM: mxs: Add iomux support Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | iMX28: Initial support for iMX28 CPUMarek Vasut2011-11-11-0/+735
| | | | | | | | | | | | | | | | | | | | | | | | This patch supports: - Timers - Debug UART - Clock Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | SPL: Allow ARM926EJS to avoid compiling in the CPU support codeMarek Vasut2011-11-08-0/+6
| | | | | | | | | | | | | | | | | | | | This allows the SPL to avoid compiling in the CPU support code. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Scott Wood <scottwood@freescale.com>
* | arm: a320: fix broken timerPo-Yu Chuang2011-11-08-84/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | timer.c used static data and are called before relocation. Move all static variables into global_data structure. Also cleanup timer.c from unused stubs and make it truly use 64 bit tick values. Remove reset_timer_masked() get_timer_masked() reference: arch/arm/cpu/arm926ejs/at91/timer.c Based on Reinhard Meyer <u-boot@emk-elektronik.de>'s patches 5dca710a3d7703e41da0e9894f2d71f9e25bea6b cfff263f41e32c7ba2ee9162a8cc6423eb5a8390 Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com> Tested-by: Macpaul Lin <macpaul@gmail.com>
* | arm, davinci: Fix setting of the SDRAM configuration registerChristian Riesch2011-11-08-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | da850_ddr_setup() expects the BOOTUNLOCK bit to be set in If BOOTUNLOCK is not set in this define, several configuration bits will not be writeable and the code will not work. Since the BOOTUNLOCK and TIMUNLOCK bits are not configuration options but access control bits, this patch changes the code to work irrespective of the value of these bits in CONFIG_SYS_DA850_DDR2_SDBCR. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | arm, davinci: Remove the duplication of LPSC functionsChristian Riesch2011-11-08-92/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The LPSC functions defined in arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c are replaced by those already defined in arch/arm/cpu/arm926ejs/davinci/psc.c. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | arm, davinci: Rename AM1808 lowlevel functions to DA850Christian Riesch2011-11-08-69/+69
|/ | | | | | | | | | | | | | | Rename arch/arm/cpu/arm926ejs/davinci/am1808_lowlevel.c and arch/arm/include/asm/arch-davinci/am1808_lowlevel.h to da850_lowlevel.c and da850_lowlevel.h since they apply not only to the AM1808 SoC but to all DA850 chips. The function names and #defines are changed likewise. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* mx53: Turn off child clocks before reconfigure perclk_rootFabio Estevam2011-11-04-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | In addition to ensuring that PERCLK remains at least 2.5 times slower than the AHB clock, certain steps need to be followed to ensure robust operation of PERCLK when reconfiguring the PERCLK clock source. To properly configure the PERCLK clock source, the following steps are required: 1.In the CCGR registers, gate the clocks to all PERCLK-dependent modules. 2.Select the desired input clock for the PERCLK root clock (to be either source from the peripherals main source clock or the lp_apm clock source). Refer to the CMCBR register, perclk_lp_apm_sel bit. 3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers to the desired setting. Refer to the CBCDR register for details. 4.In the CCGR registers, enable the desired clocks for the PERCLK-dependent module clocks. If these steps aren't followed, GPT timer may stop and the kernel stops at "Calibrating delay loop". Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* arm926ejs, davinci: add cpuinfo for dm365Heiko Schocher2011-11-03-2/+25
| | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* arm, davinci: add lowlevel function for dm365 socHeiko Schocher2011-11-03-0/+439
| | | | | | | | | | used for booting (for example) from NAND using spl code. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* arm, davinci: add support for new spl frameworkHeiko Schocher2011-11-03-1/+92
| | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap/spl: actually enable the consoleIlya Yanok2011-11-03-0/+2
| | | | | | | | | Currently OMAP SPL code does all the initialization but does not set the gd->have_console value so no output is actually performed. This patch sets gd->have_console to 1. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* arm, arm926: fix missing symbols in NAND_SPL modeHeiko Schocher2011-11-03-0/+6
| | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* arm, davinci: Add function lpsc_syncreset()Christian Riesch2011-11-03-5/+15
| | | | | | | | | | | | | This patch adds a function lpsc_syncreset that allows setting a lpsc module into Sync Reset state. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* kirkwood: drop empty asm-offsets.s fileMike Frysinger2011-11-03-0/+0
| | | | | | | This generated file does not belong in the tree -> punt. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* mx31: define pins and init for UART2 and CSPI3Helmut Raiger2011-11-03-0/+15
| | | | | Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Acked-by: Stefano Babic <sbabic@denx.de>
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