| Commit message (Collapse) | Author | Age | Lines |
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For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix
the get_ipg_per_clk function to support it.
Signed-off-by: Ye.Li <B37916@freescale.com>
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after boot.
The self-bias circuit is used by the bandgap during startup.
Once the bandgap has stabilized, the self-bias circuit should be
disabled for best noise performance of analog blocks.
Also this bit should be disabled before the chip enters STOP mode or
when ever the regular bandgap is disabled.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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THe anatop registers structure is duplicated with CCM structure at
PLL fields.
Since we are suggested not to use the name "anatop" any longer, merge
the anatop registers to the CCM structure "mxc_ccm_reg" and use CCM
to replace anatop.
Signed-off-by: Ye.Li <B37916@freescale.com>
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This problem is found when debugging QuadSPI. When "A" bit is enabled,
unaligned access will cause data abort exception. Actually, we do not
want this exception. So clear the align bit for MX6 SOCs.
Tested this code with android team colleague and did not find problem.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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The QSPI clock rate was set without disabling the clock gate, the
randomly glitch may mess up the clock and there will be no clock output,
when kernel boot up the QSPI access will fail.
To debug this issueon i.MX6SX SDB, changed the u-boot bootscript to 'sf probe; reset'
to keep rebooting, the issue can be reproduced in 20 mins, set clock out
register in CCM and measured TP86, found there is no clock ouput.
To fix this bug, disable clock gate before changing clock rate.
NOTICE: QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, need
to disable both of them.
Signed-off-by: Allen Xu <b45815@freescale.com>
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WDZST bit is write-once only bit. So we need take care the setting
in kernel ,otherwise, kernel setting will never be enabled.
Signed-off-by: Robin Gong <b38343@freescale.com>
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In ldo-bypass mode, we need trigger WDOG_B pin to reset pmic in ldo-bypass mode.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Current only set VDDARM_IN@1.175V/VDDSOC_IN@1.175V before ldo bypass switch.
So untile ldo bypass switch happened, these voltage setting is set in ldo-enable
mode. But in datasheet, we need 1.15V + 125mV = 1.275V for VDDARM_IN. We need
to downgrade cpufreq to 400Mhz and restore after ldo bypass mode switch.
Signed-off-by: Robin Gong <b38343@freescale.com>
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u-boot v2014 upstream codes have a problem in pfd reset (s_init function)
that imx6 Dual is not applied for PLL2 PFD2 reset. It is originated by
using dynamical cpu type checking and introducing two cpu types:
MXC_CPU_MX6Q and MXC_CPU_MX6D for iMX6 Dual/Quad platform.
Fixed this problem by checking the pre_periph_clk_sel and pre_periph2_clk
of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock
source, do not reset this PFD to avoid system hang.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Enable pcie support in uboot on imx6sx sd boards
- enable_pcie_clock should be call before ssp_en is set,
since that ssp_en control the phy_ref clk gate, turn on
it after the source of the pcie clks are stable.
- add debug info
- add rx_eq of gpr12 on imx6sx
- there are random link down issue on imx6sx. It's
pcie ep reset issue.
solution:reset ep, then retry link can fix it.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Add new function "arch_auxiliary_core_check_up" to check whether M4
is already up. Therefore, avoid starting M4 again when it is running.
Signed-off-by: Ye.Li <B37916@freescale.com>
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DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do
the shift after the multiply to avoid rounding errors
Signed-off-by: Andre Renaud <andre@bluewatersys.com>
(cherry picked from commit 2eb268f6fd236a5ad9d51e7e47190d7994b3920f)
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Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces
set_ldo_voltage() function that can be used to set the voltages
of any of the three LDO regulators controlled by the PMU_REG_CORE register.
Prior to this commit there was a single set_vddsoc() which only configured the
VDDSOC regulator.
Update the comments to align with the new set_ldo_voltage() implementation.
Acked-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
(cherry picked from commit 157f45da91b306d71dbf3a51325352dc11bf16d1)
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When gis enable in uboot, the CSI0 input mux select setting
to vadc module, clean the bit when gis disabled.
Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit ae66b17b7da3be50dc81ca636b67e8e879f52e26)
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The android boot needs get_board_serial function to get the
CPU uid as the serial number. Implement this function to read
the uid from fuse for all iMX6 platforms.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Since the iMX6SL does not have PCIE module, should not define the
function "imx_set_pcie_phy_power_down" for it. Otherwise, get the
build warning below:
arch/arm/cpu/armv7/mx6/soc.c:446:13: warning: 'imx_set_pcie_phy_power_down'
defined but not used [-Wunused-function]
static void imx_set_pcie_phy_power_down(void)
Signed-off-by: Ye.Li <B37916@freescale.com>
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imx6sl doesn't have the pcie module, mask the pcie
related codes from imx6sl.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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There are about 0.02% percentage on some imx6q/dl/solo
hw boards, random pcie link down when warm-reset is used.
Make sure to clear the ref_ssp_en bit16 of gpr1 before
warm-rst, and set ref_ssp_en after the pcie clks are
stable to workaround it.
rootcause:
* gpr regisers wouldn't be reset by warm-rst, while the
ref_ssp_en is required to be reset by pcie.
(work-around in u-boot)
* ref_ssp_en should be set after pcie clks are stable.
(work-around in kernel)
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Add vadc power up/down function.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add vadc clock enable function.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add registers and clock functions to enable/set LCDIF clock and LVDS.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add a new interface "mxs_lcd_panel_setup" to setup fb parameters and
specifies the LCDIF controller for multiple controllers of iMX6SX.
Pass fb parameters via "videomode" env remains work if the new interface
is not called before video initialization.
Modify LCDIF clock interface "mxs_set_lcdclk" to support multiple
LCDIF controllers on iMX6SX.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Implement the override function "arch_auxiliary_core_up" to boot
Cortex-M4 by executing command "bootaux".
The parameter "boot_private_data" points to fields where stores
the stack address and PC address for M4 to run.
Signed-off-by: Ye.Li <B37916@freescale.com>
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iMX6SX has different enet system clocks with iMX6SL, and has two ENET
controllers. So update clocks and soc APIs accordingly to support this
features.
1. Modify the clock API "enable_enet_clock" to enable enet system clock
for enet controllers.
2. Enet RGMII TX clock source may come from external or internal PLL.
By default, use the external phy CLK_25M output as TX clock source.
When using internal PLL as source, the function enable_fec_anatop_clock
must be called to enable clock for each enet controller.
3. Modify the MAC address function "imx_get_mac_from_fuse" to get either
ENET MAC address.
4. Add configuration "CONFIG_FEC_MXC_25M_REF_CLK" to enable ENET 25Mhz
reference clock.
5. Modify imx6slevk BSP to fit the new APIs.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Enable the clock for QuadSPI controllers. Must be called at
initialization.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Adding clks, pinmux, memory map, etc for iMX6SoloX.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Should use the address of one register when calling "readl"/"writel".
Signed-off-by: Ye.Li <B37916@freescale.com>
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The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable.
Setting these registers must have PL310 not enabled. But when using
Plugin mode boot, the PL310 is enabled by bootrom. Thus, disable
the PL310 before this setting.
Signed-off-by: Ye.Li <B37916@freescale.com>
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shutdown vddpu and pcie phy to save power
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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-Change HDMI video mode to VGA.
-Add pixel clock fraction part setting in IPU driver,
fix video mode timing issue.
-Add overflow state clear workaround,
fix kernel hang in HDMI driver issue.
-Correct IPU clock to 264MHz.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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Support android features:
fastboot, booti command and recovery for sabresd SD, sabresd eMMC,
sabreauto SD, sabreauto NAND.
For all booting media (SD, eMMC, NAND), inherits the partitions layout
from v2009.08. Fastboot will detect the booting media to replace
hardcoding fastboot device. SATA is not supported.
FDT is supported to use the "unused" fields in bootimg header which
requires the FDT to be combined into the boot.img.
For non-FDT boot.img, the "unused" fields should left to NULL and is
compatible to boot.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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fastboot
Android fastboot leans on the USB gadget driver to communicate with host. Porting
the imx_udc driver from v2009.08 with two changes: adding resource/memory release
APIs and replacing the uncached memory with cache flush&invalidate operations.
Pins and Clocks initialization are added to support boards:
mx6qdlsabresd, mx6qdlsabreauto, mx6slevk
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz,
enable LDO bypass and setup PMIC voltages. LDO bypass is dependent
on the flatten device tree file.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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Support HAB authentication of kernel or secondary images via bootm
or hab_auth_img u-boot command.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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Support CPU temperature sensors on i.MX6 SoC.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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Conflicts:
arch/arm/cpu/arm926ejs/mxs/Makefile
include/configs/trats.h
include/configs/trats2.h
include/mmc.h
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Since Kbuild was introduced, warmboot_avp.o has been compiled
without -march=armv4t.
Makefile should be adjusted to pass a per-file option.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
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U-Boot has supported two kinds of asm-offsets.h.
One is generic for all architectures and its source is located at
./lib/asm-offsets.c.
The other is SoC specific and its source is under SoC directory.
The problem here is that only boards with SoC directory can use
the asm-offsets infrastructure.
Putting asm-offsets.c right under CPU directory does not work.
Now a new demand is coming. PowerPC folks want to use asm-offsets.
But no PowerPC boards have SoC directory.
It seems inconsistent that some boards add asm-offsets.c to SoC
directoreis and some to CPU directories.
It looks more reasonable to put asm-offsets.c under arch/$(ARCH)/lib.
This commit merges asm-offsets.c under SoC directories into
arch/$(ARCH)/lib/asm-offsets.c.
By the way, I doubt the necessity of some entries in asm-offsets.c.
I am leaving refactoring to the board maintainers.
Please check "TODO" in the comment blocks in
arch/{arm,nds32}/lib/asm-offsets.c.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Yuantian Tang <Yuantian.Tang@freescale.com>
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U-Boot uses the 'mkimage' tool to produce various image types,
not only uImage image type. Rename the invocation name from
UIMAGE to MKIMAGE.
The following command was used to do the replacement:
git grep 'quiet_cmd_mkimage.* = UIMAGE' | cut -d : -f 1 | \
xargs -i sed -i "s@\(quiet_cmd_mkimage\)\(.*\) = UIMAGE @\1\2 = MKIMAGE@" {}
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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This patch add gicv3 support to uboot armv8 platform.
Changes for v2:
- rename arm/cpu/armv8/gic.S with arm/lib/gic_64.S
- move smp_kick_all_cpus() from gic.S to start.S, it would be
implementation dependent.
- Each core initialize it's own ReDistributor instead of master
initializeing all ReDistributors. This is advised by arnab.basu
<arnab.basu@freescale.com>.
Signed-off-by: David Feng <fenghua@phytium.com.cn>
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When flush the d$ with set/way instruction, it need calculate the way's
offset = log2(Associativity); but in current uboot's code, it use below
formula to calculate the offset: log2(Associativity * 2 - 1), so finally
it cannot flush data cache properly.
Signed-off-by: Leo Yan <leoy@marvell.com>
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Full cache line writes to the same memory region from at least two
processors might deadlock the processor. Exists on r1, r2, r3
revisions.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
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A short loop including a DMB instruction might cause a denial of
service on another processor which executes a CP15 broadcast operation.
Exists on r1, r2, r3, r4 revisions.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
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When SoC first boots up, we should invalidate the cache but not flush it.
We can use the same function for invalid and flush mostly, with a wrapper.
Invalidating large cache can ben slow on emulator, so we postpone doing
so until I-cache is enabled, and before enabling D-cache.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>
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If D-cache is enabled, we need to flush it, and invalidate i-cache before
jumping to the new location. This should be done right after relocation.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>
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Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with
sub-architecture.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>
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Avoids "could not find output section .gnu.hash" ld.bfd errors on openSUSE.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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Clock Manager driver will be called to reconfigure all the
clocks setting based on user input. The input are passed to
Preloader through handoff files
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
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This patch adds the groundwork for generating signed BootStream, which
can be used by the HAB library in i.MX28. We are adding a new target,
u-boot-signed.sb , since the process for generating regular non-signed
BootStream is much easier. Moreover, the signed bootstream depends on
external _proprietary_ _binary-only_ tool from Freescale called 'cst',
which is available only under NDA.
To make things even uglier, the CST or HAB mandates a kind-of circular
dependency. The problem is, unlike the regular IVT, which is generated
by mxsimage, the IVT for signed boot must be generated by hand here due
to special demands of the CST. The U-Boot binary (or SPL binary) and IVT
are then signed by the CST as a one block. But here is the problem. The
size of the entire image (U-Boot, IVT, CST blocks) must be appended at
the end of IVT. But the size of the entire image is not known until the
CST has finished signing the U-Boot and IVT. We solve this by expecting
the CST block to be always 3904B (which it is in case two files, U-Boot
and the hand-made IVT, are signed in the CST block).
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
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