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* ARM: move -march=* and -mtune= options to arch/arm/MakefileMasahiro Yamada2015-03-27-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | My main motivations for this commit are: [1] Follow the arch/arm/Makefile style of Linux Kernel [2] Maintain compiler options systematically Currently, we give -march=* and -mtune=* options inconsistently: Only some of the CPUs pass -march=* and -mtune=* options. By collecting such options into the single place arch/arm/Makefile we can tell which options are missing at a glance. [3] Prepare for deprecating arch/*/cpu/*/config.mk Note: This commit just moves the compiler options so as not to change the behavior at all. It does not care about the correctness of the given options. Fox example, "-march=armv5te" might be better than "-march=armv4" for ARM946EJS, but it is beyond the scope this commit. Also, filling the missing -march=* and -tune=* is left to follow-up patches. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* remove unnecessary version.h includesRob Herring2015-03-24-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-03-10-0/+45
|\ | | | | | | | | | | | | Conflicts: README Signed-off-by: Tom Rini <trini@konsulko.com>
| * Errata/ARM57: Add basic constructs to handle and apply A57 specific erratasBhupesh Sharma2015-01-31-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic constructs in the ARMv8 u-boot code to handle and apply Cortex-A57 specific erratas. As and example, the framework showcases how erratas 833069, 826974 and 828024 can be handled and applied. Later on this framework can be extended to include other erratas. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* | armv8/vexpress64: make multientry conditionalLinus Walleij2015-03-09-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the Freescale ARMv8 board LS2085A will enter U-Boot both on a master and a secondary (slave) CPU, this is not the common behaviour on ARMv8 platforms. The norm is that U-Boot is entered from the master CPU only, while the other CPUs are kept in WFI (wait for interrupt) state. The code determining which CPU we are running on is using the MPIDR register, but the definition of that register varies with platform to some extent, and handling multi-cluster platforms (such as the Juno) will become cumbersome. It is better to only enable the multiple entry code on machines that actually need it and disable it by default. Make the single entry default and add a special ARMV8_MULTIENTRY KConfig option to be used by the platforms that need multientry and set it for the LS2085A. Delete all use of the CPU_RELEASE_ADDR from the Vexpress64 boards as it is just totally unused and misleading, and make it conditional in the generic start.S code. This makes the Juno platform start U-Boot properly. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | arm64: Add Xilinx ZynqMP supportMichal Simek2015-03-02-0/+87
| | | | | | | | | | | | | | | | | | Add basic Xilinx ZynqMP arm64 support. Serial and SD is supported. It supports emulation platfrom ep108 and QEMU. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | drivers/mc: Migrated MC Flibs to 0.5.2J. German Rivera2015-02-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree from "fsl,dprcr" to "fsl-mc". Print MC version info when appropriate. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | armv8/fsl-lsch3: Add support for second DDR clockYork Sun2015-02-24-2/+15
| | | | | | | | | | | | | | | | FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for general DDR controlers, and another clock for DP-DDR. DDR driver needs to change to support multiple clocks. Signed-off-by: York Sun <yorksun@freescale.com>
* | armv8/fsl-lsch3: Add fdt-fixup for clock frequency of the DUART nodesBhupesh Sharma2015-02-24-0/+5
| | | | | | | | | | | | | | | | This patch adds the fdt-fixup logic for the clock frequency of the NS16550A related device tree nodes. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stackYork Sun2015-02-24-60/+95
| | | | | | | | | | | | | | | | | | | | | | | | Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com>
* | ARMv8/fsl-lsch3: Patch cpu node properties in DT for online coresArnab Basu2015-02-24-9/+23
| | | | | | | | | | | | | | | | U-Boot should only add "enable-method" and "cpu-release-address" properties to the "cpu" node of the online cores. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* | armv8/fsl-lsch3: Change normal memory shareabilityYork Sun2015-02-24-3/+3
| | | | | | | | | | | | | | According to hardware implementation, a single outer shareable global coherence group is defined. Inner shareable has not bee enabled. Signed-off-by: York Sun <yorksun@freescale.com>
* | fsl-ch3/lowlevel: TZPC and TZASC programming to configure non-secure accessesBhupesh Sharma2015-02-24-0/+54
|/ | | | | | | | | | | | | This patch ensures that the TZPC (BP147) and TZASC-400 programming happens for LS2085A SoC only when the desired config flags are enabled and ensures that the TZPC programming is done to allow Non-secure (NS) + secure (S) transactions only for DCGF registers. The TZASC component is not present on LS2085A-Rev1, so the TZASC-400 config flag is turned OFF for now. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ARM: armv8: Fix typo in commentaryMichal Simek2015-01-14-1/+1
| | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* kbuild: use SoC-specific CONFIG to descend into SoC directoryMasahiro Yamada2014-11-23-1/+1
| | | | | | Use "obj-$(CONFIG_FOO) += foo/" where it is possible. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* kbuild: Descend into SOC directory from CPU directoryMasahiro Yamada2014-11-23-0/+2
| | | | | | | | | Some CPUs of some architectures have SOC directories. At present, the build system directly descends into SOC directories from the top Makefile, but it should generally descend into each directory from its parent directory. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* kconfig: arm: move "armv8" define to arch/arm/KconfigMasahiro Yamada2014-11-13-6/+0
| | | | | | | | | | Commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs) collected the default values of CONFIG_SYS_CPU into arch/arm/Kconfig. This commit moves "armv8" to there for consistency. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Georges Savoundararadj <savoundg@gmail.com>
* armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot PageYork Sun2014-09-25-81/+385
| | | | | | | | | | Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
* kconfig: armv8: move CONFIG_ARM64 to KconfigMasahiro Yamada2014-09-16-0/+6
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board supportYork Sun2014-07-04-1/+1
| | | | | | | | | | | | | | | | LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* armv8/fsl-lsch3: Add support to load and start MC FirmwareJ. German Rivera2014-07-03-0/+11
| | | | | | | | | | | | | | | | Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
* ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun2014-07-03-1/+705
| | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
* ARMv8: Adjust MMU setupYork Sun2014-07-03-30/+20
| | | | | | | Make MMU function reusable. Platform code can setup its own MMU tables. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
* arm64: zero cntvoff_el2Mark Rutland2014-06-09-1/+1
| | | | | | | | | | | | | | | | | | | Currently cntvoff_el2 is initialised with an arbitrary bag of bits derived from the initial value of cnthctl_el2 on the current CPU. This is somewhat odd and problematic as some of these bits are UNKNOWN at reset and may differ across CPUs (which may cause an OS at EL1 to observe time going backwards across CPUs). This patch instead initialises cntvoff_el2 with xzr, giving the register a consistent value of zero on all CPUs. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Scott Wood <scottwood@freescale.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Tom Rini <trini@ti.com> Acked-by: David.Feng <fenghua@phytium.com.cn>
* Arm64 fix a bug of vbar_el3 initializationDavid Feng2014-05-25-2/+2
| | | | Signed-off-by: David Feng <fenghua@phytium.com.cn>
* arm64 patch: gicv3 supportDavid Feng2014-04-08-114/+39
| | | | | | | | | | | | | | This patch add gicv3 support to uboot armv8 platform. Changes for v2: - rename arm/cpu/armv8/gic.S with arm/lib/gic_64.S - move smp_kick_all_cpus() from gic.S to start.S, it would be implementation dependent. - Each core initialize it's own ReDistributor instead of master initializeing all ReDistributors. This is advised by arnab.basu <arnab.basu@freescale.com>. Signed-off-by: David Feng <fenghua@phytium.com.cn>
* ARMv8: fix bug for flush data cache by set/wayLeo Yan2014-04-07-3/+1
| | | | | | | | | When flush the d$ with set/way instruction, it need calculate the way's offset = log2(Associativity); but in current uboot's code, it use below formula to calculate the offset: log2(Associativity * 2 - 1), so finally it cannot flush data cache properly. Signed-off-by: Leo Yan <leoy@marvell.com>
* armv8/cache: Change cache invalidate and flush functionYork Sun2014-04-07-20/+46
| | | | | | | | | | | When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
* armv8/cache: Flush D-cache, invalidate I-cache for relocationYork Sun2014-04-07-6/+0
| | | | | | | | If D-cache is enabled, we need to flush it, and invalidate i-cache before jumping to the new location. This should be done right after relocation. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
* armv8/cache: Consolidate setting for MAIR and TCRYork Sun2014-04-07-25/+19
| | | | | | | | Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with sub-architecture. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
* arm: Switch to -mno-unaligned-access when supported by the compilerTom Rini2014-02-26-4/+1
| | | | | | | | | | | | | | | | | | When we tell the compiler to optimize for ARMv7 (and ARMv6 for that matter) it assumes a default of SCTRL.A being cleared and unaligned accesses being allowed and fast at the hardware level. We set this bit and must pass along -mno-unaligned-access so that the compiler will still breakdown accesses and not trigger a data abort. To better help understand the requirements of the project with respect to unaligned memory access, the Documentation/unaligned-memory-access.txt file has been added as doc/README.unaligned-memory-access.txt and is taken from the v3.14-rc1 tag of the kernel. Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Mans Rullgard <mans@mansr.com> Signed-off-by: Tom Rini <trini@ti.com>
* arm64: core supportDavid Feng2014-01-09-0/+1050
Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn>
generated by cgit v1.1 at 2024-11-18 21:18:49 +0000