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* armv8: fix #if around spin-table code in start.SOded Gabbay2017-01-14-1/+1
| | | | | | | | | | Using CONFIG_IS_ENABLED() doesn't work in SPL. This patch replaces the only occurrence of CONFIG_IS_ENABLED() in start.S to a regular #if defined(). It also adds "&& !defined(CONFIG_SPL_BUILD)" to that #if statement because the spin-table code can't currently work in SPL, and the spin-table file isn't even compiled in SPL. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
* Merge tag 'xilinx-for-v2017.03' of git://www.denx.de/git/u-boot-microblazeTom Rini2017-01-11-1/+91
|\ | | | | | | | | | | | | | | | | | | Xilinx changes for v2017.03 - ATF handoff - DT syncups - gem: Use wait_for_bit(), add simple clk support - Simple clk driver for ZynqMP - Other small changes
| * ARM64: zynqmp: Generate handoff structure for ATFMichal Simek2017-01-10-1/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx ATF extending options for passing images from BL2(FSBL) to BL31. U-Boot SPL is FSBL replacement that's why it should generate handoff structure the same. Support only one entry which is U-Boot in EL2 itself. When FIT image is adopted structure generate should be data driven. Currently ATF is placing this structure at the beggining of OCM which is rewriting early parts of ATF which should be unused at that time. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynqmp: Make SYS_VENDOR configurableMike Looijmans2017-01-10-0/+1
| | | | | | | | | | | | | | Add a string description for SYS_VENDOR to allow configuring boards from other vendors than just "xilinx". Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2017-01-10-3/+61
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| * ARM: boot0 hook: remove macro, include whole header fileAndre Przywara2017-01-04-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For prepending some board specific header area to U-Boot images we were so far including a header file with a macro definition containing the actual header specification. This works fine if there are just a few statements and if there is only one alternative. However adding more complex code quickly gets messy with this approach, so let's just drop that intermediate macro and let the #include actually insert the code directly. This converts the callers and the callees, but doesn't change anything at this point. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Steve Rae <steve.rae@raedomain.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * armv8: move reset branch into boot hookAndre Przywara2017-01-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The boot0 hook we have so far is applied _after_ the initial branch to the "reset" entry point. An upcoming change requires even this branch to be changed, so we apply the hook macro at the earliest point, and have the branch in the hook file as well. This is no functional change at this point, just refactoring to simplify upcoming patches. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * armv8: add simple sdelay implementationAndre Przywara2017-01-04-0/+14
| | | | | | | | | | | | | | | | | | The sunxi DRAM setup code needs an sdelay() implementation, which wasn't defined for armv8 so far. Shamelessly copy the armv7 version and adjust it to work in AArch64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * armv8: add lowlevel_init.SAndre Przywara2017-01-04-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | For boards that call s_init() when the SPL runs, we are expected to setup an early stack before calling this C function. Implement the proper AArch64 version of this based on the ARMv7 code. This allows sunxi boards to setup the basic peripherals even with a 64-bit SPL. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to KconfigYork Sun2017-01-04-5/+0
| | | | | | | | | | | | | | | | Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing usage in ls102xa and fsl-layerscape. Remove all powerpc macros in config header and board header files. Signed-off-by: York Sun <york.sun@nxp.com>
* | arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to KconfigYork Sun2017-01-04-0/+41
| | | | | | | | | | | | Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
* | fsl_ddr: Move DDR config options to driver KconfigYork Sun2017-01-04-50/+7
| | | | | | | | | | | | | | | | | | Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
* | crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to KconfigYork Sun2017-01-04-0/+2
| | | | | | | | | | | | | | Use Kconfig option to set little- or big-endian access to secure boot and trust architecture. Signed-off-by: York Sun <york.sun@nxp.com>
* | crypto: Move SYS_FSL_SEC_COMPAT into driver KconfigYork Sun2017-01-04-0/+4
|/ | | | | | | Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC and ARM SoCs, move it to Kconfig under the driver. Signed-off-by: York Sun <york.sun@nxp.com>
* ARM64: zynqmp: Add missing SPL dependency for boot.bin generationMichal Simek2016-12-20-0/+1
| | | | | | | boot.bin file is generated only when SPL is selected. Reflect this depency in Kconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARMv8: LS1043A: Enable LS1043A default PSCI supportmacro.wave.z@gmail.com2016-12-15-0/+21
| | | | | | | | | | A most basic PSCI implementation with only one psci_version is added for LS1043A, this can verify the generic PSCI framework, and more platform specific implementation will be added later. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARMv8: Setup PSCI memory and device treemacro.wave.z@gmail.com2016-12-15-1/+32
| | | | | | | | | Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARMv8: Add basic PSCI frameworkmacro.wave.z@gmail.com2016-12-15-0/+297
| | | | | | | | | | This patch introduces a generic ARMv8 PSCI framework, with all functions returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each platform to implement their own functions based on this framework. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARMv8: Add secure sections for PSCI text and datamacro.wave.z@gmail.com2016-12-15-0/+89
| | | | | | | | | | | | | This patch adds secure_text, secure_data and secure_stack sections for ARMv8 to hold PSCI text and data, and it is based on the legacy implementation of ARMv7. ARMV8_SECURE_BASE defines the address for PSCI secure sections, ARMV8_PSCI and ARMV8_PSCI_NR_CPUS are firstly used in this patch, so they are introduce here in Kconfig too. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definitionmacro.wave.z@gmail.com2016-12-15-5/+27
| | | | | | | | | | | | NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: QSPI: Add AHB bus 16MB+ size supportYuan Yao2016-12-05-0/+49
| | | | | | | | The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080a: Add serdes1 protocol 0x3b supportPriyanka Jain2016-12-05-0/+1
| | | | | Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl/ddr: Add erratum_a009942_check_cpo and clean related erratumShengzhou Liu2016-12-05-1/+6
| | | | | | | | | | | | | - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://git.denx.de/u-boot-mpc85xxTom Rini2016-12-04-0/+5
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| * armv8: fsl-layerscape: Move SECURE_BOOT to KconfigYork Sun2016-12-02-0/+5
| | | | | | | | | | | | Move from CONFIG_SYS_EXTRA_OPTIONS to Kconfig option. Signed-off-by: York Sun <york.sun@nxp.com>
* | ARM64: zynqmp: List secondary software boot modesMichal Simek2016-12-02-0/+12
| | | | | | | | | | | | | | | | Using alternative bootmode field to support automatic secondary boot modes. It is purely software setting where SW modes are using free bootmode combinations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Force certain bootmode for SPLMichal Simek2016-12-02-1/+1
|/ | | | | | | | ZynqMP provides an option to overwrite bootmode setting which can change SPL behavior. For example: boot SPL via JTAG and then SPL loads images from SD. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabledAlison Wang2016-11-22-0/+35
| | | | | | | | | | | As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: SMP support for loading 32-bit OSAlison Wang2016-11-22-0/+10
| | | | | | | | | | | Spin-table method is used for secondary cores to load 32-bit OS. The architecture information will be got through checking FIT image and saved in the os_arch element of spin-table, then the secondary cores will check os_arch and jump to 32-bit OS or 64-bit OS automatically. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: Support loading 32-bit OS in AArch32 execution stateAlison Wang2016-11-22-16/+76
| | | | | | | | | | | | | To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/fsl-lsch3: Update code to release secondary coresPriyanka Jain2016-11-22-5/+66
| | | | | | | | | | | | | | | NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Add NXP LS2088A SoC supportPriyanka Jain2016-11-22-2/+62
| | | | | | | | | | | | The QorIQ LS2088A SoC is built on layerscape architecture. It is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)It supports TZASC module Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape : Check SVR for initializing TZASCPriyanka Jain2016-11-22-1/+12
| | | | | | | | | | LS2080 SoC and its personalities does not support TZASC But other new SoCs like LS2088A, LS1088A supports TZASC Hence, skip initializing TZASC for Ls2080A based on SVR Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Update TZASC registers typePriyanka Jain2016-11-22-14/+14
| | | | | | | | | | | TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES are 32-bit regsiters. So while doing register load-store operations, 32-bit intermediate register, w0 should be used. Update x0 register to w0 register type. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: lsch3: Use SVR based timer base address detectionPriyanka Jain2016-11-22-0/+9
| | | | | | | | | | | | Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: lsch3: Add generic get_svr() in assemblyPriyanka Jain2016-11-22-0/+11
| | | | | Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/fsl-layerscape: Update CONFIG_LS2080A to CONFIG_FSL_LSCH3Shengzhou Liu2016-11-21-3/+4
| | | | | | | | Update CONFIG_LS2080A to CONFIG_FSL_LSCH3 to make those workaround implementing of erratum reusable for more SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Add README for deploying QSPI imageYuan Yao2016-11-21-0/+42
| | | | | | Signed-off-by: Yuan Yao <yao.yuan@nxp.com> [YS: Reviese commit subject] Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080a: Update serdes protocol supportPriyanka Jain2016-11-21-0/+6
| | | | | | | | | | | | Add these serdes protocols Serdes1: 0x39, 0x4B, 0x4C, 0x4D Serdes2: 0x47, 0x57 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> [YS: Revise commit message] Reviewed-by: York Sun <york.sun@nxp.com>
* Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini2016-11-17-4/+44
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | Patch queue for efi - 2016-11-17 Highlights this time around: - x86 efi_loader support - hello world efi test case - network device name is now representative - terminal output reports modes correctly - fix psci reset for ls1043/ls1046 - fix efi_add_runtime_mmio definition for x86 - efi_loader support for ls2080
| * armv8: fsl-layerscape: Add support for efi_loader RTS resetAlexander Graf2016-11-17-2/+31
| | | | | | | | | | | | | | | | | | | | When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: Declare spin tables as reserved for efi loaderAlexander Graf2016-11-17-0/+6
| | | | | | | | | | | | | | | | The efi loader code has its own memory map, so it needs to be aware where the spin tables are located, to ensure that no code writes into those regions. Signed-off-by: Alexander Graf <agraf@suse.de>
| * efi_loader: Disable PSCI reset for ls1043 and ls1046Alexander Graf2016-11-17-2/+3
| | | | | | | | | | | | | | The NXP ls1043 and ls1046 systems do not (yet) have PSCI enablement for reset. Don't enable generic PSCI reset code on them. Signed-off-by: Alexander Graf <agraf@suse.de>
| * efi: arm: Add aarch64 EFI app supportSimon Glass2016-11-14-0/+4
| | | | | | | | | | | | | | | | | | Add support for EFI apps on aarch64. This includes start-up and relocation code plus a link script. Signed-off-by: Simon Glass <sjg@chromium.org> [agraf: add kconfig dep] Signed-off-by: Alexander Graf <agraf@suse.de>
* | ARM64: zynqmp: Fix secondary bootmode enablingMichal Simek2016-11-15-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Do not setup use_alt bit which copy alternative boot mode to boot mode. The reason is that this bit is cleared after POR but not after any software reset which will cause that after SW reset bootrom will look for different boot image. This patch setups alternative boot mode selection (purely SW handling) and extends code to read this alternative boot mode first and use it if it is setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | tools: mkimage: Add support for initialization table for Zynq and ZynqMPMike Looijmans2016-11-15-0/+7
|/ | | | | | | | | | | | | | | | | | The Zynq/ZynqMP boot.bin file contains a region for register initialization data. Filling in proper values in this table can reduce boot time (e.g. about 50ms faster on QSPI boot) and also reduce the size of the SPL binary. The table is a simple text file with register+data on each line. Other lines are simply skipped. The file can be passed to mkimage using the "-R" parameter. It is recommended to add reg init file to board folder. For example: CONFIG_BOOT_INIT_FILE="board/xilinx/zynqmp/xilinx_zynqmp_zcu102/reg.int Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* armv8: add hooks for all cache-wide operationsStephen Warren2016-11-07-8/+22
| | | | | | | | | | | | | | SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* armv8: define get_ticks() for the ARMv8 Generic TimerAndre Przywara2016-11-05-0/+11
| | | | | | | | | | | | | | | | | | | For 64-bit ARM systems we provide just a timer_read_counter() implementation and rely on the generic non-uclass get_ticks() function in lib/time.c to call the former. However this function is actually not 64-bit safe, as it assumes a "long" to be 32-bit. Beside the fact that the resulting uint64_t isn't bigger than "long" on 64-bit architectures and thus combining two counters makes no sense, we get all kind of weird results when we try to OR in the high value shifted by _32_ bits. So let's avoid that function at all and provide a straight forward get_ticks() implementation for ARMv8, which also is in line with ARMv7. This fixes occasional immediate time-out expiration issues I see on the Pine64 board. The root cause of this needs to be investigated, but this fix looks like the right thing anyway. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* efi_loader: Rename EFI_RUNTIME_{TEXT, DATA} to __efi_runtime{, _data}Alexander Graf2016-10-19-6/+6
| | | | | | | | | | | Compiler attributes are more commonly __foo style tags rather than big upper case eye sores like EFI_RUNTIME_TEXT. Simon Glass felt quite strongly about this, so this patch converts our existing defines over to more eye friendly ones. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* efi_loader: Add generic PSCI RTSAlexander Graf2016-10-19-5/+26
| | | | | | | | | Now that we have generic PSCI reset and shutdown support in place, we can advertise those as EFI Run Time Services, allowing efi applications and OSs to reset and shut down systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
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