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path: root/arch/arm/cpu/armv8/cache_v8.c
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* armv8: mmu: split block if necessaryYork Sun2016-07-15-32/+38
* armv8: mmu: house cleaningYork Sun2016-07-15-5/+8
* arm64: Fix layerscape mmu setupAlexander Graf2016-03-21-1/+1
* arm64: Only allow dcache disabled in SPL buildsAlexander Graf2016-03-15-0/+9
* arm64: Remove non-full-va map codeAlexander Graf2016-03-15-90/+0
* thunderx: Move mmu table into board fileAlexander Graf2016-03-15-5/+3
* arm64: Make full va map code more dynamicAlexander Graf2016-03-15-55/+398
* arm64: Disable TTBR1 maps in EL1Alexander Graf2016-03-15-1/+1
* thunderx: Calculate TCR dynamicallyAlexander Graf2016-03-15-1/+58
* armv8: New MMU setup code allowing to use 48+ bits PA/VASergey Temerkhanov2016-01-19-0/+77
* armv8/layerscape: Update MMU table with execute-never bitsAlison Wang2015-11-30-2/+2
* armv8: allow custom MMU setup routines on ARMv8Stephen Warren2015-11-10-1/+1
* armv8/mmu: Set bits marked RES1 in TCRThierry Reding2015-10-15-3/+3
* armv8: fsl-lsch3: Rewrite MMU translation table entriesAlison Wang2015-09-01-4/+13
* ARM: cache: implement a default weak flush_cache() functionWu, Josh2015-08-12-8/+0
* ARM: cache: add an empty stub function for invalidate/flush dcacheWu, Josh2015-08-12-8/+0
* armv8: caches: Added routine to set non cacheable regionSiva Durga Prasad Paladugu2015-07-31-0/+36
* armv8/cache: Fix page table creationThierry Reding2015-07-28-2/+2
* armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stackYork Sun2015-02-24-7/+11
* ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun2014-07-03-1/+6
* ARMv8: Adjust MMU setupYork Sun2014-07-03-30/+20
* armv8/cache: Change cache invalidate and flush functionYork Sun2014-04-07-1/+2
* armv8/cache: Consolidate setting for MAIR and TCRYork Sun2014-04-07-3/+19
* arm64: core supportDavid Feng2014-01-09-0/+219
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