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* OMAP3: am35x: add musb functionsIlya Yanok2012-11-20-0/+76
| | | | | | AM35XX specific functions for integrated USB PHY/MUSB IP. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* am33xx: init OTG hardware and new musb gadget driverIlya Yanok2012-11-20-0/+93
| | | | | | | | AM33xx has support for dual port MUSB OTG controller. This patch adds initialization for the controller using new MUSB gadget driver and ether gadget. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* socfpga/spl: Remove malloc.hVikram Narayanan2012-11-04-1/+0
| | | | | | Remove unused header Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
* socfpga/spl: Remove timer_init from spl_board_initVikram Narayanan2012-11-04-3/+0
| | | | | | | | Timer is initialized already in board_init_r function in (common/spl/spl.c) No need to initialize it again Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Cc: Dinh Nguyen <dinguyen@altera.com>
* Merge remote-tracking branch 'u-boot-ti/master'Albert ARIBAUD2012-11-03-13/+50
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| * omap3: Rework board.c for !CONFIG_SYS_L2CACHE_OFFTom Rini2012-10-30-13/+15
| | | | | | | | | | | | | | When CONFIG_SYS_L2CACHE_OFF is defined we end up with a few warnings currently. Re-order functions so that we don't have that anymore. Signed-off-by: Tom Rini <trini@ti.com>
| * am33xx: Enable UART{1,2,3,4,5} clocksAndrew Bradford2012-10-25-0/+35
| | | | | | | | | | | | | | | | If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232 cape or the am335x_evm daughterboard, enable the required clocks for the UART in use. Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
* | Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2012-10-27-43/+117
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| * | MX5: fix warning in clock.cStefano Babic2012-10-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch fix warnings compiling with ELDK-4.2: clock.c: In function 'get_standard_pll_sel_clk': clock.c:341: warning: 'freq' may be used uninitialized in this function Reported-by : Marek Vasut <marex@denx.de> Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | mx5: Add workaround for ARM erratum ID 468414Fabio Estevam2012-10-17-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the software workaround for ARM erratum ID 468414. According to mx53/mx51 errata document: "ENGcm11133 - ARM: NEON load data can be incorrectly forwarded to a subsequent request Description: Under very specific set of conditions, data from a Neon load request can be incorrectly forwarded to a subsequent, unrelated memory request. The conditions are as follows: • Neon loads and stores must be in use • Neon L1 caching must be disabled • Trustzone must be configured and in use • The secure memory address space and the non-secure memory address space both use the same physical addresses, either as an alias or the same memory location or for separate memory locations The issue is reported by ARM, erratum ID 468414, Category 2" Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx5: lowlevel_init.S: Fix PLL settings for mx53Fabio Estevam2012-10-17-33/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the requested frequency. Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its maximum frequency. Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little bit to allow easier comparison with the original clock setup from FSL U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mx5: lowlevel_init.S: Split init_clock macroFabio Estevam2012-10-17-30/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | init_clock is currently shared between mx51 and mx53 and it contains lots of ifdef's which makes it really hard to follow the code. Split the init_clock between mx51 and mx53 to allow easier readability. No functional changes are made. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | Merge remote-tracking branch 'u-boot-ti/master'Albert ARIBAUD2012-10-26-340/+54
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| * | am33xx: support board specific ddr settingsPeter Korsgaard2012-10-25-103/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the hardcoded ddr2/ddr3 settings for the ti boards to board code, so other boards can use different types/timings. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> [trini: Make apply with rtc32k_enable() in the file] Signed-off-by: Tom Rini <trini@ti.com>
| * | am33xx: move generic parts of pinmux handling out from board/ti/am335xPeter Korsgaard2012-10-25-0/+34
| | | | | | | | | | | | | | | | | | So they are available for other boards. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
| * | am33xx/board: use cpu_mmc_init() for default mmc initializationPeter Korsgaard2012-10-25-2/+2
| | | | | | | | | | | | | | | | | | So platforms can override it with board_mmc_init() if needed. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
| * | am33xx: move ti i2c baseboard header handling to board/ti/am335x/Peter Korsgaard2012-10-25-261/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The i2c header is specific to ti(-derived) boards, and not generic for all am335x boards. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> [trini: Make re-apply with rtc32k_enable() applied] Signed-off-by: Tom Rini <trini@ti.com>
| * | am33xx/board.c: make wdtimer/uart_base staticPeter Korsgaard2012-10-25-2/+4
| | | | | | | | | | | | | | | | | | Only used here (and uart_base only for SPL). Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
| * | am33xx: Add SPI SPL as an optionTom Rini2012-10-25-0/+1
| | | | | | | | | | | | | | | | | | | | | Add the required config.mk logic for this SoC as well as the BOOT_DEVICE define. Finally, enable the options on the am335x_evm. Signed-off-by: Tom Rini <trini@ti.com>
| * | am335x: Enable RTC 32K OSC clockVaibhav Hiremath2012-10-25-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support low power state, you must source kernel system timers to persistent clock, available across suspend/resume. In case of AM335x device, the only source we have is, RTC32K, available in wakeup/always-on domain. Having said that, during validation it has been observed that, RTC clock need couple of seconds delay to stabilize the RTC OSC clock; and such a huge delay is not acceptable in kernel especially during early init and also it will impact quick/fast boot use-cases. So, RTC32k OSC enable dependency has been shifted to SPL/first-bootloader. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
| * | am33xx: Enable DDR3 for DDR3 version of beagleboneJoel A Fernandes2012-10-23-2/+7
| |/ | | | | | | | | | | | | | | | | DDR3 support is tested and working with beaglebone hardware. Include a check for this board type and configure DDR3. The timings and other configuration match EVM SK. Signed-off-by: Joel A Fernandes <joelagnel@ti.com> Acked-by: Jason Kridner <jdk@ti.com>
* | common: Add .u_boot_list into all linker filesMarek Vasut2012-10-22-0/+5
|/ | | | | | | | | | Add section for the linker-generated lists into all possible linker files, so that everyone can easily use these lists. This is mostly a mechanical adjustment. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Mike Frysinger <vapier@gentoo.org>
* mx5: Optimize lowlevel_init code sizeBenoît Thébaudeau2012-10-15-53/+59
| | | | | | | | | | | | | | | Optimize mx5 lowlevel_init.S code size: - Compute values at compile time rather than at runtime where possible. - Assign r4 to hold the zero value rather than setting registers to 0 again and again. - Associate a function to setup_pll rather than expanding its large macro code multiple times. - Allocate constant values in section only if used. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mx5/6 clocks: Fix SDHC clocksBenoît Thébaudeau2012-10-15-0/+46
| | | | | | | | | | | | | | | | The i.MX5 eSDHC clocks were considered as coming from the IPG clock although they have dedicated clock paths. Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
* mx51: Fix I2C clock ID checkBenoît Thébaudeau2012-10-15-1/+5
| | | | | | | There are only 2 I²C instances on i.MX51, but 3 on i.MX53. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5 clocks: Fix MXC_FEC_CLKBenoît Thébaudeau2012-10-15-3/+2
| | | | | | | | | The FEC clock does not come from PLL1, but from the IPG clock. The previous code was even inconsistent with itself, returning the IPG clock as expected for imx_get_fecclk(), but the PLL1 clock for mxc_get_clock(MXC_FEC_CLK). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5 clocks: Simplify imx_get_cspiclk()Benoît Thébaudeau2012-10-15-20/+3
| | | | | | | | | The code handling the dividers was duplicated for each possible input clock, and this function can benefit from the newly introduced get_standard_pll_sel_clk() function instead of duplicating this mux handling code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5 clocks: Fix get_uart_clk()Benoît Thébaudeau2012-10-15-12/+24
| | | | | | | | | | | | This function returned 66500000 instead of the correct lp_apm clock frequency if the CCM.CSCMR1.uart_clk_sel mux is set to 3. This patch fixes this issue by introducing the get_standard_pll_sel_clk() function that will be used by future patches to handle identical muxes used by many other clocks. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5 clocks: Fix get_ipg_per_clk()Benoît Thébaudeau2012-10-15-3/+7
| | | | | | | | | | | This fixes the "IPG PERCLK" frequency printed by the clocks command. The issue was that get_ipg_per_clk() used periph_clk instead of lp_apm in the case CCM.CBCMR.perclk_lp_apm_sel is set. It also fixes I²C support. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5 clocks: Fix get_periph_clk()Benoît Thébaudeau2012-10-15-20/+22
| | | | | | | | | | In the case periph_clk comes from periph_apm_clk, the latter is selected by the CCM.CBCMR.periph_apm_sel mux, which can source the lp_apm clock from its input ♯2. get_periph_clk() returned 0 instead of the lp_apm clock frequency in this case. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5 clocks: Fix get_lp_apm()Benoît Thébaudeau2012-10-15-1/+23
| | | | | | | | | | | | If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024. In that case: - on i.MX51, this clock comes from the output of the FPM, - on i.MX53, this clock comes from the output of PLL4. This patch fixes the code accordingly. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5 clocks: Add and use CCSR definitionsBenoît Thébaudeau2012-10-15-11/+23
| | | | | | | This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx51: Fix USB PHY clocksBenoît Thébaudeau2012-10-15-7/+18
| | | | | | | | | | | | | | | The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks have different clock gate control bit-fields. The existing code was correct only for i.MX53, so this patch fixes the i.MX51 use case. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Jana Rapava <fermata7@gmail.com> Cc: Wolfgang Grandegger <wg@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il>
* mx5: Fix clock gate valuesBenoît Thébaudeau2012-10-15-12/+15
| | | | | | | | | The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one of these bits like what was done is wrong and can lead to unpredictable behavior depending on the original value of these bit-fields. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5: Use explicit clock gate namesBenoît Thébaudeau2012-10-15-7/+8
| | | | | | | | Use clock gate definitions having names showing clearly the gated clock instead of names giving only a register field index. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5 clocks: CleanupBenoît Thébaudeau2012-10-15-146/+91
| | | | | | | | | | Clean up the i.MX5 clock driver: - Use readl() and writel() instead of their __raw_ counterparts. - Use the clr/setbits_le32() family of macros rather than expanding code. - Use accessor macros for bit-fields instead of _MASK and _OFFSET. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5/6: Define default SoC input clock frequenciesBenoît Thébaudeau2012-10-15-36/+29
| | | | | | | | | | | Define default SoC input clock frequencies for i.MX5/6 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Liu <r64343@freescale.com> Cc: Matt Sealey <matt@genesi-usa.com> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* imx: Use MXC_I2C_CLK in imx i2c driverMatthias Weisser2012-10-15-0/+2
| | | | | | | | i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using MXC_I2C_CLK on all imx systems using i2c. Signed-off-by: Matthias Weisser <weisserm@arcor.de> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX6: get rid of redundant struct src_regs (dupe of struct src)Eric Nelson2012-10-15-1/+1
| | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fieldsEric Nelson2012-10-15-4/+6
| | | | | | | | | | | | | Add meaningful constants for each clock channels and use them for enabling and disabling i.MX6 clocks. Includes an update to enable/disable the IPU1 clock in drivers/video/ipu_common to remove IMX5x register access when used on i.MX6 as discussed in V1: http://patchwork.ozlabs.org/patch/185129/ Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* Tegra20: Move some include files to arch-tegra for sharing with Tegra30Tom Warren2012-10-15-6/+6
| | | | | | | | | | | The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h. Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20' 'root' file. All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK. Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra20: Move some code files to common directories for upcoming Tegra30 ↵Tom Warren2012-10-15-1/+48
| | | | | | | | | | | | | | | | patches. Move files that are going to be common between T20 and T30 into 'tegra-common' subdirs in AVP (arm720t), CPU (armv7), and shared (arch/arm/cpu/.) areas. Any files that are left behind in '/tegra20' will be copied to '/tegra30' subdirs and modified for that SoC. The 'common' files should need only minor changes. Include files (arch/arm/include/asm/arch-tegra/tegra20) will be done in a follow-on patch. Builds fine w/MAKEALL -s tegra20. Checkpatch.pl is clean. Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: add USB ULPI init codeLucas Stach2012-10-15-22/+131
| | | | | | | | | | | | | This adds the required code to set up a ULPI USB port. It is mostly a port of the Linux ULPI setup code with some tweaks added for more correctness, discovered along the way of debugging this. To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT have to be set in the board configuration file. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* tegra20: port to new ehci interfaceLucas Stach2012-10-15-11/+4
| | | | | | | EHCI interface now supports more than one controller. Wire up our usb functions to use this new interface. Signed-off-by: Lucas Stach <dev@lynxeye.de>
* ARM: prevent misaligned array initsAlbert ARIBAUD2012-10-15-2/+5
| | | | | | | | | | | | | | Under option -munaligned-access, gcc can perform local char or 16-bit array initializations using misaligned native accesses which will throw a data abort exception. Fix files where these array initializations were unneeded, and for files known to contain such initializations, enforce gcc option -mno-unaligned-access. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> [trini: Switch to usign call cc-option for -mno-unaligned-access as Albert had done previously as that's really correct] Signed-off-by: Tom Rini <trini@ti.com>
* arm: armv7: omap3: Fix restore sequence in lowlevel_initAlbert ARIBAUD2012-10-08-5/+4
| | | | | | | | | | | The restore sequence in lowlevel_init was in the wrong order, causing lr to lose its original value and be set equal to ip instead. Also, its use of the stack clashes with that of s_init, so move the s_init call after the restore and turn it into a tail-optimized branch. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* arm: rmobile: bugfix: wrong register saving in lowlevel_initTetsuyuki Kobayashi2012-10-08-11/+1
| | | | | | | | lowlevel_init() of rmobile badly assumed that ip register holds return address. The commit "63ee53a7 armv7 cpu_init_crit: Simplify code" breaks this assumption. This patch removes this bad assumption and simplify code. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
* arm: armv7: temporarily set -mno-unaligned-accessAlbert ARIBAUD2012-10-05-0/+2
| | | | | | | | | This patch aims at ensuring that the 2012.10 release works out-of-the-box on as many targets as possible, by reinstating commit 5347560f5427bcdd48a563b62180481606ac8044, which adds option -mno-unaligned-access to armv7 builds. This patch will be overriden immediately after release of 2012.10.
* ARM: Add Altera SOCFPGA Cyclone5Dinh Nguyen2012-10-04-0/+410
| | | | | | | | | | | | | | | | | Add minimal support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Chin Liang See <clsee@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Tom Trini <trini@ti.com> Cc: Wolfgang Denx <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> ---- v8: Remove no_return attribute for reset_cpu Based on v2012.10-rc2
* arm: Support new Xilinx Zynq platformMichal Simek2012-10-04-0/+232
| | | | | | | | | Add timer driver. Signed-off-by: Michal Simek <monstr@monstr.eu> CC: Joe Hershberger <joe.hershberger@gmail.com> CC: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
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