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* omap3:clock: check cpu_family before enabling clks for IVA & CAMVaibhav Hiremath2011-09-04-4/+10
| | | | | | | | | | | In case of AM3517 and AM3505 (which is OMAP3 varients), IVA2 and ISP-CAMERA modules have been removed. So add check for cpu_family before enabling clocks for these modules, else this impacts subsequent power consumption and system suspend/resume functionality. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap3:clock: configure GFX clock to 200MHz for AM/DM37xVaibhav Hiremath2011-09-04-1/+1
| | | | | | | | | | | | AM/DM37x is another OMAP3 variant, where the GFX clock has been boosted to 192MHz/200MHz. So fix the GFX_DIV value for this change. HW Errata: Due to dependency of TV out clock of 54MHz, it is not possible to configure GFX to 192MHz. So as per HW errats, the recommended GFX clock is 200MHz (=CORE_CLK/2). Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* armv7: cache: remove flush on un-aligned invalidateAneesh V2011-09-04-6/+8
| | | | | | | | | | Remove the flush of boundary cache-lines done as part of invalidate on a non cache-line boundary aligned buffer Also, print a warning when this situation is recognized. Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: stronger barrier for cache-maintenance operationsAneesh V2011-09-04-6/+6
| | | | | | | | set-way operations need a DSB after them to ensure the operation is complete. DMB may not be enough. Use DSB after all operations instead of DMB. Signed-off-by: Aneesh V <aneesh@ti.com>
* omap: enable caches at system start-upAneesh V2011-09-04-0/+16
| | | | Signed-off-by: Aneesh V <aneesh@ti.com>
* Tegra2: Use clock and pinmux functions to simplify codeSimon Glass2011-09-04-33/+14
| | | | Signed-off-by: Simon Glass <sjg@chromium.org>
* Tegra2: Add additional pin multiplexing featuresSimon Glass2011-09-04-1/+53
| | | | | | | This adds an enum for each pin and some functions for changing the pin muxing setup. Signed-off-by: Simon Glass <sjg@chromium.org>
* Tegra2: Add more clock supportSimon Glass2011-09-04-36/+176
| | | | | | This adds functions to enable/disable clocks and reset to on-chip peripherals. Signed-off-by: Simon Glass <sjg@chromium.org>
* Tegra2: Add microsecond timer functionSimon Glass2011-09-04-6/+12
| | | | | | | These functions provide access to the high resolution microsecond timer and tidy up a global variable in the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* MX: MX35 / MX5: uniform clock command with powerpcStefano Babic2011-09-04-2/+2
| | | | | | | | | | | There was already a command to show the processor clocks for PowerPC (clocks). For i.MX, the "clockinfo" command was introduce. The patch sets the same command name used on PowerPC. A nasty and not needed newline is also dropped in the help for the command. Signed-off-by: Stefano Babic <sbabic@denx.de>
* ARM: MX51: PLL errata workaroundDavid Jander2011-09-04-0/+38
| | | | | | | | | | | | | This is a port of the official PLL errata workaround from Freescale to mainline u-boot. The PLL's in the i.MX51 processor can go out of lock due to a metastable condition in an analog flip-flop when used at high frequencies. This workaround implements an undocumented feature in the PLL (dither mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. Signed-off-by: David Jander <david@protonic.nl>
* omap: fix gpio related build breaksAneesh V2011-09-04-3/+3
| | | | | Signed-off-by: Aneesh V <aneesh@ti.com> Acked-by: Dirk Behme <dirk.behme@googlemail.com>
* omap4: clock init support for omap4460Aneesh V2011-08-03-7/+54
| | | | | Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: support TPS programmingAneesh V2011-08-03-7/+62
| | | | | | | | | | | TPS62361 is the new power supply used in OMAP4460 that supplies vdd_mpu. VCORE1 from Phoenix supplies vdd_core and VCORE2 supplies vdd_iva. VCORE3 is not used in OMAP4460. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap: reuse omap3 gpio support in omap4Aneesh V2011-08-03-27/+42
| | | | | Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: sdram init changes for omap4460Aneesh V2011-08-03-17/+22
| | | | | Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: add omap4460 revision detectionAneesh V2011-08-03-0/+3
| | | | | Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* mkimage: Add OMAP boot image supportJohn Rigby2011-08-03-0/+30
| | | | | | | | | | - Add mkimage support for OMAP boot image - Add support for OMAP boot image(MLO) generation in the new SPL framework Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap: add MMC and FAT support to SPLAneesh V2011-08-03-2/+252
| | | | | | | | | | | | | | - Add MMC raw and FAT mode boot support for OMAP - Provide a means by which parameters passed by ROM-code can be saved in u-boot. - Save boot mode related information passed by OMAP4 ROM-code and use it to determine where to load the u-boot from - Assumes that the image has a mkimage header. Gets the payload size and load address from this header. If the header is not detected assume u-boot.bin as payload Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap: add basic SPL supportAneesh V2011-08-03-2/+198
| | | | | | | | | | | | | - Provide alternate implementations of board_init_f() board_init_r() for OMAP spl. - Provide linker script - Initialize global data - Add serial console support - Update CONFIG_SYS_TEXT_BASE to allow for SPL's bss and move it to board config header from config.mk Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* armv7: start.S: fixes and enhancements for SPLAneesh V2011-08-03-12/+39
| | | | | | | | | | | - Allow SPL to have .bss disjoint from rest of the image - Allow for .bss setup in CONFIG_SPL_BUILD case too. - Take care of the special case where relocation offset = 0. - Compile out exception handling code and install a simpler vector Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: automatic sdram detectionAneesh V2011-08-03-0/+238
| | | | | | | | | | | | | | | | | | | | | | | | | Identify SDRAM devices connected to EMIF automatically: LPDDR2 devices have some Mode Registers that provide details about the device such as the type, density, bus width etc. EMIF has the capability to read these registers. If there are no devices connected to a given chip-select reading mode registers will return junk values. After reading as many such registers as possible and matching with expected ranges of values the driver can identify if there is a device connected to the respective CS. If we identify that a device is connected the values read give us complete details about the device. This along with the base AC timings specified by JESD209-2 allows us to do a complete automatic initialization of SDRAM that works on all boards. Please note that the default AC timings specified by JESD209-2 will be safe for all devices but not necessarily optimal. However, for the Elpida devices used on Panda and SDP the default timings are both safe and optimal. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: calculate EMIF register valuesAneesh V2011-08-03-4/+953
| | | | | | | | | | | | | | Calculate EMIF register values based on AC timing parameters from the SDRAM datasheet and the DDR frequency rather than using the hard-coded values. For a new board the user doen't have to go through the tedious process of calculating the register values. Instead, just provide the AC timings from the device data sheet as input and the driver will automatically calculate the register values. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: add sdram init supportAneesh V2011-08-03-3/+464
| | | | | | | Add support for the SDRAM controller (EMIF). Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: add clock supportAneesh V2011-08-03-0/+811
| | | | | | | | | | | | | | Add support for: 1. DPLL locking 2. Initialization of clock domains and clock modules 3. Setting up the right voltage on voltage rails This work draws upon previous work done for x-loader by: Santosh Shilimkar <santosh.shilimkar@ti.com> Rajendra Nayak <rnayak@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: add OMAP4430 revision checkAneesh V2011-08-03-0/+64
| | | | | Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: cleanup pin mux dataAneesh V2011-08-03-3/+126
| | | | | | | | | | | | | - separate mux settings into essential and non essential parts - essential part is board independent as of now(so move it to SoC directory). Will help in having single SPL for all boards. - Non-essential part(the pins not essential for u-boot to function) need to be phased out eventually. - Correct mux data by aligning to the latest settings in x-loader Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap3: Include array definition only when it is usedSanjeev Premi2011-08-03-0/+3
| | | | | | | | | | | | The array of strings corresponding to cpu revision is used only when CONFIG_DISPLAY_CPUINFO is selected - in the function print_cpuinfo(). Enclose definition of this array in #ifdef...#endif for the same. Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* Timer: Remove reset_timer_masked()Graeme Russ2011-07-26-21/+7
| | | | | | | In some circumstances, reset_timer_masked() was called be timer_init() in order to perform architecture specific timer initialisation. In such cases, the required code in reset_timer_masked() has been moved into timer_init()
* Timer: Remove reset_timer() for non-Nios2 archesGraeme Russ2011-07-26-20/+0
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* Timer: Remove set_timer completelyGraeme Russ2011-07-26-25/+0
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* replace CONFIG_PRELOADER with CONFIG_SPL_BUILDAneesh V2011-07-26-3/+3
| | | | | | replace all occurences of CONFIG_PRELOADER with CONFIG_SPL_BUILD Signed-off-by: Aneesh V <aneesh@ti.com>
* ARM: MX5: Fix broken leftover TO-2 errata workaroundDavid Jander2011-07-18-1/+5
| | | | | | | | This check was broken. r3 does not contain the silicon revision anymore, so we need to reload it. Also, this errata only applies to i.MX51. Signed-off-by: David Jander <david@protonic.nl> Acked-by: Stefano Babic <sbabic@denx.de>
* ARM: add missing CONFIG_SKIP_LOWLEVEL_INIT for armv7Rob Herring2011-07-17-0/+2
| | | | | | | | cpu_init_crit can be skipped, but the code is still enabled requiring a platform to supply lowlevel_init. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Albert ARIBAUD <albert.aribaud@free.fr>
* MX5: Update to autogenerated asm-offsets.hStefano Babic2011-07-14-0/+78
| | | | | | | On i.MX5, the asm-offsets.h file is not yet generated as it should be. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Matthias Weisser <weisserm@arcor.de>
* MX5: Introduce a function for setting the chip select sizeFabio Estevam2011-07-04-0/+30
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* OMAP[34]: fix broken timerJohn Rigby2011-07-04-3/+4
| | | | | | | | | | | | | | | | | | | | As implemented now the timer used to implement __udelay counts to 0xffffffff and then gets stuck there because the the programmed reload value is 0xffffffff. This value is not only wrong but illegal according to the reference manual. One can reproduce the bug by leaving a board at the u-boot prompt for sometime then issuing a sleep command. The sleep will hang forever. The timer is a count up timer that reloads as it rolls over from 0xffffffff so the correct load value is 0. Change TIMER_LOAD_VAL from 0xffffffff to 0 and introduce a new constant called TIMER_OVERFLOW_VAL set to 0xffffffff. Signed-off-by: John Rigby <john.rigby@linaro.org> Tested-by: Igor Grinberg <grinberg@compulab.co.il>
* armv7: adapt s5pc1xx to the new cache maintenance frameworkAneesh V2011-07-04-82/+6
| | | | | | adapt s5pc1xx to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: adapt omap3 to the new cache maintenance frameworkAneesh V2011-07-04-283/+149
| | | | | | adapt omap3 to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: adapt omap4 to the new cache maintenance frameworkAneesh V2011-07-04-0/+21
| | | | | | adapt omap4 to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: integrate cache maintenance supportAneesh V2011-07-04-27/+38
| | | | | | | | | | - Enable I-cache on bootup - Enable MMU and D-cache immediately after relocation - Do necessary initialization before enabling d-cache and MMU - Changes to cleanup_before_linux() - Make changes according to the new framework Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: rename cache related CONFIG flagsAneesh V2011-07-04-3/+0
| | | | | | | | | | | | | | | | Replace the cache related CONFIG flags with more meaningful names. Following are the changes: CONFIG_L2_OFF -> CONFIG_SYS_L2CACHE_OFF CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF Signed-off-by: Aneesh V <aneesh@ti.com> V2: * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE V4: * Changed all three flags to the final names suggested as above and accordingly changed the commit message
* armv7: cache maintenance operations for armv7Aneesh V2011-07-04-1/+395
| | | | | | | | | | | | | | | | | | | | | | | | | | - Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU - Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache - D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache - Add maintenance functions for TLB, branch predictor array etc. - Enable -march=armv7-a so that armv7 assembly instructions can be used Signed-off-by: Aneesh V <aneesh@ti.com>
* Minor coding style cleanupWolfgang Denk2011-06-02-3/+3
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* armv7: Add ST-Ericsson u8500 archJohn Rigby2011-06-01-0/+291
| | | | | | | | Based on ST-Ericsson internal git repo. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> CC: Albert Aribaud <albert.aribaud@free.fr>
* S5PC2XX: clock: support pwm clock for evt1 (cpu revision 1)Minkyu Kang2011-05-26-20/+26
| | | | | | | The source of pwm clock is fixed at evt1. And some registers for pwm clock are removed. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* S5P: add set_mmc_clk for external clock controlJaehoon Chung2011-05-26-0/+37
| | | | | | | | | | | This patch added set_mmc_clk for external clock control. c210 didn't support host clock control. So We need external_clock_control function for c210. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* S5PC2XX: Support the cpu revisionMinkyu Kang2011-05-26-0/+2
| | | | | | | | S5PC210 SoC have two cpu revisions, and have some difference. So, support the cpu revision for each revision. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* S5P:SROM config code moved to s5p-common directoryChander Kashyap2011-05-26-13/+13
| | | | | | | | | SROM config code is made common for S5P series of boards. smdkc100.c now refers to s5p-common/sromc.c for SROM related subroutines. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* MX53: Handle silicon revision 2.1 caseFabio Estevam2011-05-23-7/+3
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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