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* ARM: DRA7: Update DDR IO configurationLokesh Vutla2015-06-12-4/+8
| | | | | | | | DDRIO_2 and LPDDR2CH1_1 registers are not present for DRA7. So not configuring these registers for DRA7xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA72-evm: Enable HW levelingLokesh Vutla2015-06-12-6/+11
| | | | | | | | | Updating EMIF registers to enable HW leveling on DRA72-evm. Also updating the timing registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7-evm: Enable HW levelingLokesh Vutla2015-06-12-6/+16
| | | | | | | | Updating EMIF registers to enable HW leveling on DRA7-evm. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: DDR3: Add support for HW levelingLokesh Vutla2015-06-12-24/+198
| | | | | | | | DRA7 EMIF supports Full leveling for DDR3. Adding support for the Full leveling sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* dts: Disable device tree for SPL on all boardsSimon Glass2015-06-10-0/+10
| | | | | | | We plan to enable device tree in SPL by default. Before doing this, explicitly disable it for all boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Allow cleanup_before_linux() without disabling cachesSimon Glass2015-06-10-18/+29
| | | | | | | | This function is used before jumping to U-Boot, but in that case we don't always want to disable caches. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
* sunxi: Request macpwr gpio before using itHans de Goede2015-06-10-0/+1
| | | | | | | | This fixes ethernet no longer working on boards which use a gpio to enable the phy. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-06-08-0/+7
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| * arm: vf610: Add clock support for DSPIBhuvanchandra DV2015-06-08-0/+7
| | | | | | | | Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
* | sunxi: usb_phy: Swap check for disconnect thresholdHans de Goede2015-06-04-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit the code for determining the disconnect threshold was checking for sun4i or sun6i assuming that those where the exception and that newer SoCs use a disconnect threshold of 2 like sun7i does. But it turns out that newer SoCs actually use a disconnect threshold of 3 and sun5i and sun7i are the exceptions, so check for those instead. Here are the settings from the various Allwinner SDK sources: sun4i-a10: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun5i-a13: USBC_Phy_Write(usbc_no, 0x2a, 2, 2); sun6i-a31: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun7i-a20: USBC_Phy_Write(usbc_no, 0x2a, 2, 2); sun8i-a23: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun8i-h3: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun9i-a80: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); Note this commit makes no functional changes for sun4i - sun7i, and changes the disconnect threshold for sun8i to match what Allwinner uses. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2015-06-01-0/+22
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| * | arm: rmobile: alt: Update to QoS revision 0.31 and 0.321Nobuhiro Iwamatsu2015-06-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This updates r8a7794 QoS to revision 0.31 for ES1 and revision 0.321 for ES2. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: gose: Update to QoS revision 0.311Nobuhiro Iwamatsu2015-06-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This updates r8a7793 QoS to revision 0.311. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: koelsch: Update to QoS revision 0.411Nobuhiro Iwamatsu2015-06-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This updates r8a7791 QoS to revision 0.411. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: lager: Update to QoS revision 0.973Nobuhiro Iwamatsu2015-06-01-0/+22
| |/ | | | | | | | | | | | | | | | | This updates r8a7790 QoS to revision 0.973. This commit can changed from KConfig to fit contents of the QoS. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ARM: sunxi: Share sun6i PSCI backend with sun8iChen-Yu Tsai2015-05-29-0/+5
| | | | | | | | | | | | | | | | | | sun8i can share the PSCI backend with sun6i. Only difference is sun8i does not have CPU power clamp controls. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: sunxi: Add sun6i specific PSCI implementationChen-Yu Tsai2015-05-29-0/+277
| | | | | | | | | | | | | | | | | | This adds PSCI support for sun6i. So far it only supports the PWR_ON method. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: sunxi: Make PSCI code sun7i specificChen-Yu Tsai2015-05-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | The PSCI code only works for sun7i. Rename it with _sun7i suffix, and build only if building for sun7i. This paves the way for adding PSCI support for other platforms. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: sunxi: Document registers in PSCI codeChen-Yu Tsai2015-05-29-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | The PSCI CPU_ON code accesses quite a few registers. Document their names to make it easier to cross reference. Also explain "lock cpu" and "unlock cpu" as enabling/disabling debug access. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memoryDaniel Kochmański2015-05-29-2/+12
| | | | | | | | | | | | | | | | | | | | | | This commit adds support to the sunxi SPL to load u-boot from the internal NAND. Note this only adds support to access the boot partitions to load u-boot, full NAND support to load the kernel, etc. from the nand data partition will come later. Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sun9i: Basic sun9i (A80) supportHans de Goede2015-05-29-0/+9
| | | | | | | | | | | | | | Add initial sun9i (A80) support, only uart + mmc are supported for now. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Remove support for building "old-fashioned" fel binariesHans de Goede2015-05-29-8/+0
| | | | | | | | | | | | | | | | | | | | The latest versions of the fel tool support loading normal u-boot builds directly, and this is now the preferred way to use the fel boot method. This commit removes support for the old deprecated standalone fel builds. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Use axp221 sid on a33Hans de Goede2015-05-29-5/+3
|/ | | | | | | | | Unlike the A31 and the A23 the A33 actually has a SID inside the SoC again, but sid[3] is 0 (at least on some SoCs), so it is better to use the axp221 sid. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-05-26-12/+103
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| * arm, imx6, i2c: add I2C4 for MX6DLHeiko Schocher2015-05-26-11/+22
| | | | | | | | | | | | add I2C4 modul for MX6DL based boards. Signed-off-by: Heiko Schocher <hs@denx.de>
| * imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTPTim Harvey2015-05-19-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480 in the Fusemap Description Table in the reference manual. Return this value as well as min/max temperature based on the value. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. This has been tested with IMX6 Automative and Industrial parts. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: mx6: add get_cpu_speed_grade_hz func to return MHz speed grade from OTPTim Harvey2015-05-19-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description Table. Return this frequency so that it can be used elsewhere. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * arm: mx6: ddr: set fast-exit on DDR3 if pd_fast_exit specifiedTim Harvey2015-05-19-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support to the MMDC however enabling it on the DDR3 got missed. Make sure we enable it on the DDR3 as well. Gateworks uses Micron memory as well as Winbond in MX6. We have found in testing that we need to enable fast-exit for Winbond stability. Gateworks boards are currently the only boards using the MX6 SPL and enabling fast-exit mode. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | sunxi: Make DRAM_ODT_EN Kconfig setting a boolHans de Goede2015-05-19-14/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make DRAM_ODT_EN Kconfig setting a bool, add a separate DRAM_ODT_CORRECTION setting for A23 SoCs and use DRAM_ODT_EN Kconfig everywhere instead of only in dram_sun4i.c and hardcoding odt_en elsewhere. Note this commit makes no functional changes for existing boards, its purpose is to allow changing the odt_en value on future A33 boards. For sun4i/sun5i/sun7i boards which set DRAM_ODT_EN=y (which no defconfigs currently do) this patch turns on odt for both the DQ and the DQS lines, whereas previously it was possibly (but not desirable) to turn odt on only for one of them by setting the in DRAM_ODT_EN option to 1 or 2 instead of 3. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
* | sunxi: Fix dram initialization not working on some a33 devicesHans de Goede2015-05-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | When porting the allwinner dram init code to u-boot we missed some code setting an extra bit when doing auto dram config. This commits add this bit, fixing dram init not working on the ga10h 10" a33 tablet which I'm bringing up atm. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: add support for UART2 on A23/A33Laurent Itti2015-05-19-0/+4
| | | | | | | | | | | | | | | | | | | | Add support for UART2 (2-pin version but note that RTS/CTS pins are available pn that port for possible future use), can be selected in config by using CONFIG_CONS_INDEX=3 Signed-off-by: Laurent Itti <laurentitti@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge git://git.denx.de/u-boot-samsungTom Rini2015-05-18-28/+37
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| * exynos: clock: clean up checkpatch issuesMinkyu Kang2015-05-18-28/+37
| | | | | | | | Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | arm: mx6: ddr3: Remove dead codeNikolay Dimitrov2015-05-15-22/+0
| | | | | | | | | | | | | | imx6 mmdc supports data rates up to 1066 MT/s, so remove the code handling higher data rates. Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
* | mx6: Set shared override bit in PL310 AUX_CTRL registerFabio Estevam2015-05-15-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having bit 22 cleared in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. This was inspired by a patch from Catalin Marinas [1] and also from recent discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring suggested that bootloaders should initialize the cache. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html [2] https://lkml.org/lkml/2015/2/20/199 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
* | arm: mx6: Clamp MMDC and DDR3 clocks for timing calculationsNikolay Dimitrov2015-05-15-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported frequencies as per imx6 SOC models, and for dynamically calculating valid clock value based on mem_speed. Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which doesn't take into account DDR3 memory limitations. Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com>
* | tegra: Boot in non-secure mode by defaultJan Kiszka2015-05-13-1/+1
| | | | | | | | | | | | | | | | | | | | Upstream Linux is broken with default configs when PSCI, thus non-secure mode is enabled. So the user should explicitly enable this mode, e.g. when she disabled CONFIG_CPU_IDLE in Linux (in which case it's safe to use). We can revert this workaround once Linux got fixed. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0Ian Campbell2015-05-13-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: Add board-specific initialization hook for PSCIJan Kiszka2015-05-13-0/+6
| | | | | | | | | | | | | | | | Tegra boards will have to initialize power management for the PSCI support this way. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | virt-dt: Allow reservation of secure region when in a RAM carveoutJan Kiszka2015-05-13-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In this case the secure code lives in RAM, and hence the memory node in the device tree needs to be adjusted. This avoids that the OS will map and possibly access the reservation. Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out such a region. We only support cutting off memory from the beginning or the end of a RAM bank as we do not want to increase their number (which would happen if punching a hole) for simplicity reasons This will be used in a subsequent patch for Jetson-TK1. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: Put target PC for PSCI CPU_ON on per-CPU stackJan Kiszka2015-05-13-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a per-CPU variable for saving the target PC during CPU_ON operations. This allows us to run this service independently on targets that have more than 2 cores and also core-local power control. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: Factor out reusable psci_get_cpu_stack_topJan Kiszka2015-05-13-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | This algorithm will be useful on Tegra as well, plus we will need it for making _psci_target_pc per-CPU. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: Factor out reusable psci_cpu_entryJan Kiszka2015-05-13-18/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | _sunxi_cpu_entry can be converted completely into a reusable psci_cpu_entry. Tegra124 will use it as well. As with psci_disable_smp, also the enabling is designed to be overloaded in cased SMP is not controlled via ACTLR. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: Factor out reusable psci_cpu_off_commonJan Kiszka2015-05-13-62/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely cache disabling and flushing, clrex and the disabling of SMP for the dying CPU. These steps are apparently generic for ARMv7 and will be reused for Tegra124 support. As the way of disabled SMP is not architectural, though commonly done via ACLTR, the related function can be overloaded. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: Factor out common psci_get_cpu_idJan Kiszka2015-05-13-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Will be required for obtaining the ID of the current CPU in shared PSCI functions. The default implementation requires a dense ID space and only supports a single cluster. Therefore, the functions can be overloaded in cases where these assumptions do not hold. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditionsJan Kiszka2015-05-13-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those. CC: Tang Yuantian <Yuantian.Tang@freescale.com> CC: York Sun <yorksun@freescale.com> CC: Steve Rae <srae@broadcom.com> CC: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | arch: Make board selection choices optionalJoe Hershberger2015-05-12-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | By making the board selections optional, every defconfig will include the board selection when running savedefconfig so if a new board is added to the top of the list of choices the former top's defconfig will still be correct. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com>
* | ARM: socfpga: abolish CONFIG_SOCFPGAMasahiro Yamada2015-05-07-1/+1
| | | | | | | | | | | | Replace CONFIG_SOCFPGA with CONFIG_ARCH_SOCFPGA. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: socfpga: move SoC sources to mach-socfpgaMasahiro Yamada2015-05-07-1876/+0
| | | | | | | | | | | | Our recent trend is to collect SoC files into arch/arm/mach-(SOC). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: socfpga: remove redundant config.mkMasahiro Yamada2015-05-07-8/+0
| | | | | | | | | | | | | | | | Because all the SOCFPGA boards define CONFIG_SPL_FRAMEWORK (see include/configs/socfpga_common.h), u-boot.img is automatically added to the target image list by the top Makefile. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-11-12 00:44:41 +0000