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| * imx6: clock: Enable External Memory Interface [EIM] clock (eim_slow_clock)Lukasz Majewski2016-11-30-0/+14
| | | | | | | | | | | | | | | | This patch extends the imx6 clock code to enable or disable the EIM slow clock, which in necessary when one wants to use EIM interface t o read/write from external memory (e.g. NOR). Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
| * mx6sx: Add initial support for Samtec VIN|ING 2000 boardChristoph Fritz2016-11-30-0/+7
| | | | | | | | | | | | | | | | This patch adds initial support for Samtec VIN|ING 2000 board. Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Acked-by: Marek Vasut <marex@denx.de>
| * mx6sx: Add initial support for UDOO Neo BoardBreno Lima2016-11-29-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UDOO Neo Board is a development board from Seco that has three models: - UDOO Neo Basic - UDOO Neo Basic Kick Starter - UDOO Neo Extended - UDOO Neo Full All versions are based on the i.MX6 SoloX processor. For more details about the UDOO Neo board, please refer to: http://www.udoo.org/udoo-neo/ This work is based on a previous commit of Francesco Montefoschi <francesco.monte@gmail.com>: https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed574961844 Only tested on the UDOO Neo Full board. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routinesEric Nelson2016-11-29-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR calibration routines are gated by conditionals for the i.MX6DQ SOCs, but with the use of the sysinfo parameter, these are usable on at least i.MX6SDL and i.MX6SL variants with DDR3. Also, since only the Novena board currently uses the dynamic DDR calibration routines, these routines waste space on other boards using SPL. Add a KConfig entry to allow boards to selectively include the DDR calibration routines. Signed-off-by: Eric Nelson <eric@nelint.com>
| * mx6: ddr: add routine to return DDR calibration dataEric Nelson2016-11-29-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | Add routine mmdc_read_calibration() to return the output of DDR calibration. This can be used for debugging or to aid in construction of static memory configuration. This routine will be used in a subsequent patch set adding a virtual "mx6memcal" board, but could also be useful when gathering statistics during an initial production run. Signed-off-by: Eric Nelson <eric@nelint.com>
| * mx6: ddr: pass mx6_ddr_sysinfo to calibration routinesEric Nelson2016-11-29-42/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR calibration routines have scattered support for bus widths other than 64-bits: -- The mmdc_do_write_level_calibration() routine assumes the presence of PHY1, and -- The mmdc_do_dqs_calibration() routine tries to determine whether one or two DDR PHYs are active by reading MDCTL. Since a caller of these routines must have a valid struct mx6_ddr_sysinfo for use in calling mx6_dram_cfg(), and the bus width is available in the "dsize" field, use this structure to inform the calibration routines which PHYs are active. This allows the use of the DDR calibration routines on CPU variants like i.MX6SL that only have a single MMDC port. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * mx6: ddr: allow 32 cycles for DQS gating calibrationEric Nelson2016-11-29-0/+7
| | | | | | | | | | | | | | | | | | | | | | The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample cycle) for the first PHY. Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0 output value isn't polluted with calibration artifacts. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2016-11-29-15921/+0
| |\ | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: update the REFTOP_VBGADJ settingPeng Fan2016-11-16-5/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to design team, we need to set REFTOP_VBGADJ in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the actually table is as below: '000" - set REFTOP_VBGADJ[2:0] to 3'b000 '001" - set REFTOP_VBGADJ[2:0] to 3'b001 '010" - set REFTOP_VBGADJ[2:0] to 3'b010 '011" - set REFTOP_VBGADJ[2:0] to 3'b011 '100" - set REFTOP_VBGADJ[2:0] to 3'b100 '101" - set REFTOP_VBGADJ[2:0] to 3'b101 '110" - set REFTOP_VBGADJ[2:0] to 3'b110 '111" - set REFTOP_VBGADJ[2:0] to 3'b111 Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
| * | imx: mx6sx: Disable ENET clock before switching clock parentYe.Li2016-11-16-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Need to gate ENET clock when switching to a new clock parent, because the mux is not glitchless. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | | armv7: psci: cpu_off: flush D-Cache before disable D-CachePeng Fan2016-11-29-0/+4
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before disable cache, need to first flush cache. There maybe dirty data in D-Cache before disable D-Cache. After disable D-Cache, the first store instructions in psci_v7_flush_dcache_all will directly store registers {r4-r5, r7, r9-r11, lr} to memory. If there is dirty data before disable D-Cache, psci_v7_flush_dcache_all will flush data to memory, and may overwrite the memory that hold the registers {r4-r5, r7, r9-r11, lr}. So before disable cache, first flush D-Cache. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: York Sun <york.sun@nxp.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Tom Rini <trini@konsulko.com>
* | arm: Introduce arch/arm/mach-omap2 for OMAP2 derivative platformsTom Rini2016-11-21-15954/+0
| | | | | | | | | | | | | | | | | | | | | | This moves what was in arch/arm/cpu/armv7/omap-common in to arch/arm/mach-omap2 and moves arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2 as subdirectories. All refernces to the former locations are updated to the current locations. For the logic to decide what our outputs are, consolidate the tests into a single config.mk rather than including 4. Signed-off-by: Tom Rini <trini@konsulko.com>
* | board: ti: amx3xx: Remove multiple EEPROM readsLokesh Vutla2016-11-21-0/+3
| | | | | | | | | | | | | | Detect the board very early and avoid reading eeprom multiple times. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: AMx3xx: Centralize early clock initializationLokesh Vutla2016-11-21-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | This is similar to Commit 93e6253d11030 ("ARM: OMAP4/5: Centralize early clock initialization") that was done for OMAP4+, reflecting the same for AM33xx and AM43xx SoCs to centralize clock initialization. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Add setup_early_clocks that calls setup_clocks_for_console for ti81xx] Signed-off-by: Tom Rini <trini@konsulko.com>
* | ARM: AMx3xx: Allow arch specific code to use early DMLokesh Vutla2016-11-21-6/+20
|/ | | | | | | | | | | | Early system initialization is being done before initf_dm is being called in U-Boot. Then system will fail to boot if any of the DM enabled driver is being called in this system initialization code. So, rearrange the code a bit so that DM enabled drivers can be called during early system initialization. This is inspired by commit e850ed82bce8 ("ARM: OMAP4+: Allow arch specific code to use early DM") Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* sunxi: Rename CONFIG_SUNXI to CONFIG_ARCH_SUNXIJagan Teki2016-10-30-1/+1
| | | | | | | | | | | | CONFIG_SUNXI -> CONFIG_ARCH_SUNXI and removed CONFIG_SUNIX from config_whitelist.txt Cc: Simon Glass <sjg@chromium.org> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* engicam: icorem6: Add DM_GPIO, DM_MMC supportJagan Teki2016-10-26-0/+2
| | | | | | | | | | | Add DM_GPIO, DM_MMC support for u-boot and disable for SPL. Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* arm: imx6q: Add devicetree support for Engicam i.CoreM6 DualLite/SoloJagan Teki2016-10-26-0/+1
| | | | | | | | | | | | | | | | | | | | i.CoreM6 DualLite/Solo modules are system on module solutions manufactured by Engicam with following characteristics: CPU NXP i.MX6 DL, 800MHz RAM 1GB, 32, 64 bit, DDR3-800/1066 NAND SLC,512MB Power supply Single 5V MAX LCD RES FULLHD and more info at http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial supportJagan Teki2016-10-26-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot Log for i.CoreM6 DualLite/Solo Starter Kit: ----------------------------------------------- U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46) Trying to boot from MMC1 U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530) CPU: Freescale i.MX6SOLO rev1.3 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 31C Reset cause: POR DRAM: 256 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device switch to partitions #0, OK mmc0 is current device reading boot.scr ** Unable to read file boot.scr ** reading zImage 6741808 bytes read in 341 ms (18.9 MiB/s) Booting from mmc ... reading imx6dl-icore.dtb 30600 bytes read in 19 ms (1.5 MiB/s) Booting using the fdt blob at 0x18000000 Using Device Tree in place at 18000000, end 1800a787 Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0 Boot Log for i.CoreM6 Quad/Dual Starter Kit: -------------------------------------------- U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46) Trying to boot from MMC1 U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530) CPU: Freescale i.MX6Q rev1.2 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 28C Reset cause: POR DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-10-12-3/+90
|\ | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/ls1021aqds.h include/configs/ls1021atwr.h
| * armv7: ls1021a: Move DDR config options to KconfigYork Sun2016-10-06-0/+47
| | | | | | | | | | | | | | | | Move DDR3, DDR4 and related config options to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: Move SYS_FSL_SRDS_* and SYS_HAS_SERDES to KconfigYork Sun2016-10-06-0/+11
| | | | | | | | | | | | | | Move these options to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: Move SYS_FSL_IFC_BANK_COUNT to KconfigYork Sun2016-10-06-0/+5
| | | | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. This option is also used by PowerPC SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: Move MAX_CPUS to KconfigYork Sun2016-10-06-0/+11
| | | | | | | | | | | | | | | | Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This option is used by Freescale Layerscape SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: Move FSL_LSCH2 FSL_LSCH3 to KconfigYork Sun2016-10-06-0/+8
| | | | | | | | | | | | | | | | Move these options to Kconfig and create a sub-menu to avoid name conflict with other architectures. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: Fix Kconfig for proper display menuYork Sun2016-10-06-2/+3
| | | | | | | | | | | | | | | | Some config options should not have prompt. They are selected by choosing target. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * armv7: LS1021a: enable i-cache in start.SXiaoliang Yang2016-10-06-1/+5
| | | | | | | | | | | | | | | | | | | | Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First stage of u-boot can run faster after that. There is a description about skip lowlevel init in board/freescale/ls1021atwr/README. Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-10-08-35/+99
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| * | ARM: vf610: use strcpy for soc environment variableStefan Agner2016-10-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To create the soc environment variable we concatenate two strings on the stack. So far, strcat has been used for the first string as well as for the second string. Since the variable on the stack is not initialized, the first strcat may not start using the first entry in the character array. This then could lead to an buffer overflow on the stack. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| * | tools: mkimage: add support for Vybrid image formatAlbert ARIBAUD \(3ADEV\)2016-10-06-0/+5
| | | | | | | | | | | | | | | | | | | | | This format can be flashed directly at address 0 of the NAND FLASH, as it contains all necessary headers. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | imx: imx6ul: disable POR_B internal pull upPeng Fan2016-10-04-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | >From TO1.1, SNVS adds internal pull up control for POR_B, the register filed is GPBIT[1:0], after system boot up, it can be set to 2b'01 to disable internal pull up. It can save about 30uA power in SNVS mode. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: fix USB bmode to use reserved valueStefan Agner2016-10-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the bmode "usb" uses BOOT_CFG1 to 0x01, -which means BOOT_CFG1[7:4] is set to b0000. According to Table 8-7 Boot Device Selection this is NOR/OneNAND and not Reserved. Use 0x10 which leads to b0001, which is a Reserved boot device. With that the SoC reliably falls back to the serial loader. Cc: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * | arm: imx: add i.MX6ULL 14x14 EVK board supportPeng Fan2016-10-04-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX6ULL EVK board support: Add device tree file, which is copied from NXP Linux. Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR. The uart iomux settings are still keeped in board file. Boot Log: U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800) CPU: Freescale i.MX6ULL rev1.0 at 396MHz CPU: Commercial temperature grade (0C to 95C) at 15C Reset cause: POR Model: Freescale i.MX6 ULL 14x14 EVK Board Board: MX6ULL 14x14 EVK DRAM: 512 MiB MMC: initialized IMX pinctrl driver FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 => mmc dev 1 switch to partitions #0, OK mmc1 is current device Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: imx6ull: adjust the ldo 1.2v bandgap voltagePeng Fan2016-10-04-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0 bit[6:4]) setting to 2b'110. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: update clock settings and CCM register mapPeng Fan2016-10-04-22/+37
| | | | | | | | | | | | | | | | | | | | | | | | Update Clock settings and CCM register map for i.MX6ULL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: adjust POR_B setting for i.MX6ULLPeng Fan2016-10-04-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust POR_B settings on i.MX6ULL according to IC design team's suggestion: 2'b00 : always PUP100K 2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL 2'b10 : always disable PUP100K 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: misc soc updatePeng Fan2016-10-04-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update misc SOC related settings for i.MX6ULL, such as FEC mac address, cpu speed grading and mmdc channel mask clearing. Also update s_init to skip pfd reset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ul: using runtime check when configuring PMIC_STBY_REQPeng Fan2016-10-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since MX6ULL select MX6UL, we can not use IS_ENABLED(CONFIG_MX6UL) here, because this piece code is only for i.MX6UL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: skip setting ahb clockPeng Fan2016-10-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rom already initialized clock at 396M and 132M for arm core and ahb, so skip setting them again in U-Boot. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: add kconfig entry for MX6ULLYe Li2016-10-04-0/+4
| |/ | | | | | | | | | | | | | | | | i.MX6ULL is derivative from i.MX6UL, so select MX6UL for MX6ULL. If need to differenate MX6ULL from MX6UL, use CONFIG_MX6ULL Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | ARM: AM437X: Add Silicon ID supportLokesh Vutla2016-10-08-1/+4
| | | | | | | | | | | | | | | | | | | | Add silicon ID code for AM437x silicon. This can be used to print the cpu info using CONFIG_DISPLAY_CPUINFO. Also printing "CPU :" along with cpu name in order to be consistent with other OMAP platforms. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: OMAP5+: Override switch_to_hypervisor functionKeerthy2016-10-06-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | Override the switch_to_hypervisor function to switch cpu to hypervisor mode using the available ROM code hook early in the boot phase before the boot loader checks for HYP mode. Based on the work done by Jonathan Bergsagel jbergsagel@ti.com. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: Introduce function to switch to hypervisor modeKeerthy2016-10-06-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | omap: Set appropriate cache configuration for LPAE and non-LAPE casesKeerthy2016-10-06-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | Cache configuration methods is different for LPAE and non-LPAE cases. Hence the bits and the interpretaion is different for two cases. In case of non-LPAE mode short descriptor format is used and we need to set Cache and Buffer bits. In the case of LPAE the cache configuration happens via MAIR0 lookup. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | omap: Remove hardcoding of mmu section shift to 20Keerthy2016-10-06-2/+2
| | | | | | | | | | | | | | | | | | As of now the mmu section shift is hardcoded to 20 but with LPAE coming into picture this can be different. Hence replacing 20 with MMU_SECTION_SHIFT macro. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: Respect CONFIG_SPL_STACK define in lowlevel_init.SSiarhei Siamashka2016-10-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPL and U-Boot proper may use different initial stack locations, which are configured via CONFIG_SPL_STACK and CONFIG_SYS_INIT_SP_ADDR defines. The lowlevel_init.S code needs to handle this in the same way as crt0.S Without this fix, setting the U-Boot stack location to some place, which is not safely accessible by the SPL (such as the DRAM), causes a very early SPL deadlock. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | spl: Kconfig: Move SPL_DISPLAY_PRINT to KconfigSimon Glass2016-10-06-0/+6
|/ | | | | | | | Move this option to Kconfig and tidy up existing uses. Also add a function comment to the header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ti: omap-common: Allow AM33xx devices to be built securelyAndrew F. Davis2016-10-02-1/+1
| | | | | | | | | | Like OMAP54xx and AM43xx family SoCs, AM33xx based SoCs have high security enabled models. Allow AM33xx devices to be built with HS Device Type Support. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
* am33xx: config.mk: Fix option used to enable SPI SPL image typeAndrew F. Davis2016-10-02-2/+2
| | | | | | | | | | | | | The option SPL_SPI_SUPPORT is used to enable support in SPL for loading images from SPI flash, it should not be used to determine the build type of the SPL image itself. The ability to read images from SPI flash does not imply the SPL will be booted from SPI flash. Unconditionally build SPI flash compatible SPL images. Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* am33xx: config.mk: Add support for additional secure boot image typesAndrew F. Davis2016-10-02-2/+18
| | | | | | | | | | | | | | Depending on the boot media, different images are needed for secure devices. The build generates u-boot*_HS_* files as appropriate for the different boot modes. For AM33xx devices additional image types are needed for various SPL boot modes as the ROM checks for the name of the boot mode in the file it loads. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
generated by cgit v1.1 at 2024-11-10 02:44:11 +0000