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* arch/arm/cpu/armv7/omap-common/clocks-common.c: Fix build warningsAnatolij Gustschin2012-03-29-3/+1
| | | | | | | | | | | | | Fix: clocks-common.c: In function 'setup_non_essential_dplls': clocks-common.c:323:6: warning: variable 'sys_clk_khz' set but not used [-Wunused-but-set-variable] clocks-common.c: In function 'setup_non_essential_dplls': clocks-common.c:323:6: warning: variable 'sys_clk_khz' set but not used [-Wunused-but-set-variable] Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Tom Rini <trini@ti.com>
* sdrc.c: Fix typo in do_sdrc_init() for SPLTom Rini2012-03-29-1/+1
| | | | | | We need to setup CS0 and CS1 not CS0 and CS0 again. Signed-off-by: Tom Rini <trini@ti.com>
* tegra: Enhance clock support to handle 16-bit clock divisorsSimon Glass2012-03-29-22/+41
| | | | | | | | I2C ports have a 16-bit clock divisor. Add code to handle this special case so that I2C speeds below 150KHz are supported. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Rename NV_PA_PMC_BASE to TEGRA2_PMC_BASESimon Glass2012-03-29-6/+6
| | | | | | | | | Change this name to fit with the current convention in the Tegra header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: Add support for Tegra USB peripheralSimon Glass2012-03-29-1/+463
| | | | | | | | | | | | | | | | | | This adds basic support for the Tegra2 USB controller. Board files should call board_usb_init() to set things up. Configuration is performed through the FDT, with aliases used to set the order of the ports, like this fragment: aliases { /* This defines the order of our USB ports */ usb0 = "/usb@0xc5008000"; usb1 = "/usb@0xc5000000"; }; drivers/usb/host files ONLY: Acked-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: fdt: Add function to return peripheral/clock IDSimon Glass2012-03-29-0/+58
| | | | | | | | | A common requirement is to find the clock ID for a peripheral. This is the second cell of the 'clocks' property (the first being the phandle itself). Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: fdt: Add Tegra2x device tree file from kernelSimon Glass2012-03-29-0/+2
| | | | | | | | | | | | | This was taken from commit b48c54e2 at: git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git config.mk is updated to provide this file to boards through the built-in mechanism: /include/ ARCH_CPU_DTS Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* arm: Tegra2: Fix ELDK42 gcc failure with inline asm stack pointer loadTom Warren2012-03-29-5/+5
| | | | | | | | | | | | | The 4.2.2 gcc in the ELDK42 release doesn't like the direct SP load using a constant in tegra2_start. Change it to use a load thru another reg using mov sp, %0 : : "r"(CONST). Tested on my Seaboard T20-A03, U-Boot loads and runs OK. Also compiled all tegra2 builds with both gcc 4.2.2 and 4.4.1 OK. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* ARM: highbank: add reset supportRob Herring2012-03-28-0/+1
| | | | | | | Implement reset for highbank platform. Reset is triggered via a wfi instruction, so enabling armv7 for the compiler is necessary. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* ARM: highbank: Add boot counter supportRob Herring2012-03-28-1/+37
| | | | | | Add boot counter support using an sysreg which is persistent across reset. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* ARM: highbank: fix us_to_tick calculationRob Herring2012-03-28-2/+2
| | | | | | | udelay calls were off due to failing to convert us to ns. Fix this and drop the unnecessary shifts since NS_PER_TICK is only 7ns. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* ARM: highbank: add missing get_tbclkRob Herring2012-03-28-0/+5
| | | | | | | The get_tbclk function was missing and the recent commit "common: add possibility for readline_into_buffer timeout" makes it required. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* SPL: call cleanup_before_linux() before booting LinuxStefano Babic2012-03-27-1/+1
| | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Tom Rini <tom.rini@gmail.com> CC: Wolfgang Denk <wd@denx.de> CC: Simon Schwarz <simonschwarzcor@gmail.com>
* OMAP3: SPL: do not call I2C init if no I2C is set.Stefano Babic2012-03-27-0/+2
| | | | | | | | | | Call i2c initialization in spl_board_init only if I2C is configured for the board. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Tom Rini <tom.rini@gmail.com> CC: Wolfgang Denk <wd@denx.de> CC: Simon Schwarz <simonschwarzcor@gmail.com>
* Add cache functions to SPL for armv7Stefano Babic2012-03-27-2/+2
| | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Tom Rini <tom.rini@gmail.com> CC: Wolfgang Denk <wd@denx.de> CC: Simon Schwarz <simonschwarzcor@gmail.com>
* omap/spl: change output of spl_parse_image_headerSimon Schwarz2012-03-27-1/+1
| | | | | | | | | This only outputs "Assuming u-boot.bin..." if debug is active. Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> CC: Tom Rini <tom.rini@gmail.com> CC: Stefano Babic <sbabic@denx.de> CC: Wolfgang Denk <wd@denx.de>
* omap-common/spl: Add linux boot to SPLSimon Schwarz2012-03-27-23/+74
| | | | | | | | | | | | | | | | | | | | | | | | This adds Linux booting to the SPL This depends on CONFIG_MACH_TYPE patch by Igor Grinberg (http://article.gmane.org/gmane.comp.boot-loaders.u-boot/105809) Related CONFIGs: CONFIG_SPL_OS_BOOT Activates/Deactivates the OS booting feature CONFIG_SPL_OS_BOOT_KEY defines the IO-pin number u-boot switch - if pressed u-boot is booted CONFIG_SYS_NAND_SPL_KERNEL_OFFS Offset in NAND of direct boot kernel image to use in SPL CONFIG_SYS_SPL_ARGS_ADDR Address where the kernel boot arguments are expected - this is normaly RAM-begin + 0x100 Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> CC: Tom Rini <tom.rini@gmail.com> CC: Stefano Babic <sbabic@denx.de> CC: Wolfgang Denk <wd@denx.de>
* omap-common: Add NAND SPL linux bootingSimon Schwarz2012-03-27-16/+50
| | | | | | | | | | | | | | | | This implements booting of Linux from NAND in SPL Related config parameters: CONFIG_SYS_NAND_SPL_KERNEL_OFFS Offset in NAND of direct boot kernel image to use in SPL CONFIG_SYS_SPL_ARGS_ADDR Address where the kernel boot arguments are expected - this is normally RAM-start + 0x100 (on ARM) Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> CC: Tom Rini <tom.rini@gmail.com> CC: Stefano Babic <sbabic@denx.de> CC: Wolfgang Denk <wd@denx.de>
* mx53: Make PLL2 to be the parent of UART clockFabio Estevam2012-03-27-3/+17
| | | | | | | | | | | | | | | | | | Change the parent UART clock to be PLL2, so that U-boot can also boot a Freescale 2.6.35 kernel for mx53. FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid conflicts with IPU clocks, so that the video resolution can be changed without affecting the UART clock. On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded and this patch fixes this problem. Tested on a mx53loco board booting a FSL kernel and also a mainline kernel. Reported-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* mx6: Read silicon revision from registerFabio Estevam2012-03-27-3/+29
| | | | | | | | | | | | | | | Instead of hardcoding the mx6 silicon revision, read it in run-time. Also, besides the silicon version print the mx6 variant type: quad,dual/solo or solo-lite. Tested on a mx6qsabrelite, where it shows: CPU: Freescale i.MX6Q rev1.0 at 792 MHz Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <r64343@freescale.com>
* mx6: Fix reset cause for Power On Reset caseFabio Estevam2012-03-27-0/+1
| | | | | | | | | | | | | After booting mx6qsabrelite from POR the following is reported: CPU: Freescale i.MX61 family rev1.0 at 792 MHz Reset cause: unknown reset This is because both the POR and WDOG bits are set after reset. Fix this by also checking both bits in the POR case. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* SPL: Add YMODEM over UART load supportMatt Porter2012-03-26-0/+84
| | | | | | | | | | Adds support for loading U-Boot from UART using YMODEM protocol. If YMODEM support is enabled in SPL and the romcode indicates that SPL loaded via UART then SPL will wait for start of a YMODEM transfer via the console port. Signed-off-by: Matt Porter <mporter@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* spl.c: Use __noreturn decoratorTom Rini2012-03-26-3/+2
| | | | | Acked-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Tom Rini <trini@ti.com>
* usb/ehci: Add USB support for the MX6QWolfgang Grandegger2012-03-26-0/+13
| | | | | | | Currently, only USB Host 1 is supported. Cc: Remy Bohmer <linux@bohmer.net> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
* Remove execute permissions from source filesThomas Weber2012-03-04-0/+0
| | | | Signed-off-by: Thomas Weber <weber@corscience.de>
* armv7: omap3: leave outer cache enabledAneesh V2012-02-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Mainline kernel for OMAP3 doesn't enable L2 cache It expects L2$ to be enabled by ROM-code/bootloader. Leaving L2$ enabled can be troublesome in cases where the L2 cache is not under CP15 control, such as in Cortex-A9. This problem is explained in detail in the commit dc7100f4080952798413fb63bb4134b22c57623a However, this problem doesn't apply to Cortex-A8 because L2$ in Cortex-A8 is under CP15 control and hence the generic armv7 maintenance opertions work for it. As such we can make an exception for OMAP3 and leave the L2$ enabled when we jump to kernel. This is done by removing the strongly-linked implementation of v7_outer_cache_disable() and allowing it to fall back to the weakly linked implementation that doesn't do anything. Signed-off-by: Aneesh V <aneesh@ti.com>
* MX5/MX6: add missing get_ticks() and get_tbclk()Stefano Babic2012-02-27-18/+57
| | | | | | | | | | | commit f31a911fe (arm, post: add missing post_time_ms for arm) enables get_ticks and get_tbclk for all arm based boards, MX5/MX6 have not yet implemented. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Dirk Behme <dirk.behme@de.bosch.com> CC: Jason Liu <jason.hui@linaro.org> CC: Marek Vasut <marek.vasut@gmail.com>
* OMAP4460: Reduce MPU clock speed from 920 to 700Aneesh V2012-02-12-11/+11
| | | | | | | | | | We do not have thermal management or Smartreflex enabled at U-Boot level. So, it's better to stick to OPP100 for MPU instead of the OPP Turbo that is used now. Adjust the VDD_MPU accordingly. Tested-by: Sebastien Jan <s-jan@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com>
* omap3: fix comment typosPeter Meerwald2012-02-12-2/+2
| | | | Signed-off-by: Peter Meerwald <p.meerwald@bct-electronic.com>
* OMAP4: clock-common: Move the usb dppl configuration to new funcGovindraj.R2012-02-12-21/+33
| | | | | | | | | | | usb dpll configuration is done only part of non-essential dppl configuration however if CONFIG_USB_EHCI_OMAP is defined we may have to configure usb dpll's for proper functioning of usb modules. So move the usb dppl configuration to a new func. and utilise the same during essential dpll configuration. Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Tested-by: Stefano Babic <sbabic@denx.de>
* OMAP3+: Clock: Adding ehci clock enablingGovindraj.R2012-02-12-0/+29
| | | | | | | | | | Adding ehci clock enabling mechanism part of clock framework. When essential clocks are enabled during init phase usb host clocks can also be enabled from clock framework. Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Tested-by: Stefano Babic <sbabic@denx.de>
* ARM: EXYNOS: Add support for Exynos5 based SoCsChander Kashyap2012-02-12-5/+203
| | | | | | | | Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of SoCs. This patch adds the support for Exynos5. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macroChander Kashyap2012-02-12-5/+1
| | | | | | | | | CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4) architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ to make it generic for exynos architecture. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* S5P: support generic watchdog timerMinkyu Kang2012-02-12-0/+60
| | | | | | | | This patch adds support the generic watchdog timer for s5pc1xx and exynos4 Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: HeungJun, Kim <riverful.kim@samsung.com>
* Exynos: Fix ARM Clock frequency calculationChander Kashyap2012-02-12-6/+9
| | | | | | | | | | Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calculating it as follows: ARMCLK=MOUTCORE / (DIVCORE + 1) / (DIVCORE2 + 1) Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* i.mx: i.mx5: update imx_get_mac_from_fuse functionJason Liu2012-02-12-1/+1
| | | | | | | | | | | | | | | | | | | | FEC does not work on the i.mx51/53evk board, it will hangup In: serial Out: serial Err: serial Net: After bisect, it due to the following commit: be252b6 net: imx: Add multi-FEC support for imx_get_mac_from_fuse has change the imx_get_mac_from_fuse fucntion prototype, but fail to update i.mx5, here it does it. After apply this patch, u-boot works again on i.mx51/53 evk boards. Signed-off-by: Jason Liu <jason.hui@linaro.org> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* OMAP SPL: Fix missing timer_init() call in OMAP4 s_init()Dechesne, Nicolas2012-02-12-0/+2
| | | | | | | | | | | | In 8775471bb, the call to timer_init() was removed from common code and put in OMAP3 s_init() function. As a result the boot was broken on OMAP4. This patch adds timer_init() in OMAP4 s_init(), that fix boot on all OMAP4 boards. Signed-off-by: Nicolas Dechesne <n-dechesne@ti.com> Tested-by: Robert P. J. Day <rpjday@crashcourse.ca> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rini <trini@ti.com>
* OMAP3: Correct get_sdr_cs_offset maskTom Rini2012-02-12-1/+1
| | | | | | | | | | | | The function get_sdr_cs_offset reads the CS_CFG register in the SDRC to determine where CS1 is mapped to. make_cs1_contiguous() will set CS1 to follow after CS0. The CS_CFG register has values in bits 9:8 and 3:0 but we had erroneously been testing 5:4 and 3:0 resulting in incorrect offsets on platforms with less than 128MB as 3:0 describe 128MB hunks and 9:8 describe 32MB offsets after the 128MB hunk. Tested-by: Grant Erickson <marathon96@gmail.com> Signed-off-by: Tom Rini <trini@ti.com>
* arm: omap3: Define save_boot_params in lowlevel_init.S for SPL onlyPali Rohár2012-02-12-2/+2
| | | | | | | | Wrap the function save_boot_params with CONFIG_SPL_BUILD. This will allow non-SPL boards to define their own save_boot_params functions in U-Boot itself. Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
* tegra2: Enable data cacheSimon Glass2012-02-12-0/+8
| | | | | | | | | | | | This enables the data cache on Tegra2 boards. As discussed on the list, this is better off in the Tegra2 cpu code than in a particular vendor directory. We should be safe turning on the cache for all Tegra2 boards. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add SDMMC support to funcmuxSimon Glass2012-02-12-0/+63
| | | | | | | | | This adds support for SDMMC ports to the funcmux. Only one option is supported: FUNCMUXO_SDMMC_8BIT which selects an 8-bit wide SDIO interface where available. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add I2C support to funcmuxSimon Glass2012-02-12-0/+40
| | | | | | | | Add support to funcmux for selecting I2C functions and programming the pinmux appropriately. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add enum to select from available funcmux configsSimon Glass2012-02-12-5/+6
| | | | | | | | | We want to give a name to each available funcmux config. For now we just use the pin group names (even through it is verbose) since there seems to be nothing better. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Adjust funcmux config test to permit expansionSimon Glass2012-02-12-25/+35
| | | | | | | | We want to support config options other than zero, so move the test to the end to allow intermediate code to OK such a config. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra2: Fix default RAM size selection in odmdataStephen Warren2012-02-12-1/+1
| | | | | | | | | | | | | | | | | A value of 0 in the odmdata RAM size field means default, which is 512MB not 1GB. Fix this. For reference, see: http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=blob;\ f=arch/arm/mach-tegra/odm_kit/query/harmony/tegra_devkit_custopt.h;\ h=1ec7010911454f19a5018952fd245785a62c59ad;\ hb=0e52d7fe25b11a656c376a37890be219470661fb v2: New patch Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra2: Fix conflicting pinmux for UARTAStephen Warren2012-02-12-0/+12
| | | | | | | | | | | | | | | Tegra appears to boot with function UARTA pre-selected on mux group SDB. If two mux groups are both set to the same function, it's unclear which group's pins drive the RX signals into the HW module. For UARTA, SDB certainly overrides group IRTX in practice. To solve this, configure some alternative function on SDB to avoid the conflict. Also, tri-state the group to avoid driving any signal onto it until we know what's connected. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: AM33XX: Add i2c supportPatil, Rachna2012-01-23-0/+5
| | | | | | | Add i2c driver board hookup for AM335X EVM Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Patil, Rachna <rachna@ti.com>
* omap_rev_string: output to stdoutAndreas Müller2012-01-16-14/+8
| | | | | | | | * avoid potential buffer overflows * allow SPL-build not to output "Texas Instruments Revision detection unimplemented" Signed-off-by: Andreas Müller <schnitzeltony@gmx.de> Signed-off-by: Tom Rini <trini@ti.com>
* OMAP SPL: call timer_init in s_init to make udelay work earlierAndreas Müller2012-01-16-2/+2
| | | | Signed-off-by: Andreas Müller <schnitzeltony@gmx.de>
* ARM:AM33XX: Add SPL support for AM335X EVMChandan Nath2012-01-16-107/+119
| | | | | | | | | | | This patch is added to support SPL feature on AM335X platform. In this patch, MMC1 is configured as boot device for SPL and support for other devices will be added in the next patch series. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
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