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* imx: mx6: Fixed AIPS3 base address issueYe.Li2015-02-10-1/+1
| | | | | | | | | Should use AIPS3 configuration address 0x0227C000 to set AIPS3, not the AIPS3 base address. Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to align with AIPS1 and AIPS2, and resolve the AIPS3_ARB_BASE_ADDR undefine problem. Signed-off-by: Ye.Li <B37916@freescale.com>
* imx:mx6sx add dram io configure for mx6sxPeng Fan2015-01-22-14/+82
| | | | | | | | | | | Define two structure mx6sx_iomux_ddr_regs and mx6sx_iomux_grp_regs. Add a new function mx6sx_dram_iocfg to configure dram io. Since mx6sx only have one channel mmdc0, define a new empty macro MMDC1 to replace mmdc1->entry=value for mx6sx. And to other mx6 soc, MMDC1 effects as "mmdc1->entry=value". Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2015-01-16-46/+93
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| * arm: am437x: Enable hardware leveling for EMIFJames Doublesin2015-01-13-46/+93
| | | | | | | | | | | | | | | | | | | | | | | | Switch to using hardware leveling for certain parameters on the EMIF rather than using precalculated values. Doing this also means we have a common place now between am437x and am335x for setting emif_sdram_ref_ctrl with a value for the correct delay length. Tested-by: Felipe Balbi <balbi@ti.com> Tested-by: Tom Rini <trini@ti.com> Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* | sunxi: usbc: Add support for usb-vbus0 controller by axp drivebus pinHans de Goede2015-01-14-0/+26
| | | | | | | | | | | | | | | | | | The axp221 / axp223's N_VBUSEN pin can be configured as an output rather then an input, and this is used on some boards to control usb-vbus0, add support for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: usbc: Add support for usb0 to the common usbc codeHans de Goede2015-01-14-8/+25
| | | | | | | | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Move usb-controller init code out of ehci-sunxi.c for reuse for otgHans de Goede2015-01-14-0/+230
| | | | | | | | | | | | | | | | | | | | Most of the usb-controller init code found in ehci-sunxi.c also is necessary to init the otg usb controller, so move it to a common place. While at it also update various #ifdefs / defines for sun8i support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sun7i: Move psci_arch_init close to text_endJan Kiszka2015-01-14-40/+40
| | | | | | | | | | | | | | | | | | "adr rX, text_end" only works if the label is close. Adding further code to the other functions will prevent this. So move the containing function close to label. No functional change. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sun7i: Add support for taking CPUs offline via PSCIJan Kiszka2015-01-14-0/+171
| | | | | | | | | | | | | | | | | | | | | | Based on the original version by Marc Zyngier. It adds a psci_cpu_off implementation for the A20 SoC. The mechanism works by first preparing the calling CPU to go offline (disable and flush cache, disable SMP), then requesting CPU 0 to pull the plug. The request is sent as FIQ on SGI15. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Fix PLL1 running at half speed on sun8iHans de Goede2015-01-14-2/+6
| | | | | | | | | | | | | | | | | | | | PLL1 on sun6i / sun8i also has a p factor which divides the clock by 2^p (to the power p). On sun6i the p factor is ignored, but on sun8i it is used and we were setting it to 1, resulting in the CPU running at 504 MHz instead of 1008 MHz, this commit fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Fix buggy sun6i/sun8i DRAM size detection logicSiarhei Siamashka2015-01-14-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After reboot, reset or even short power off, DRAM typically retains the old stale data for some period of time (for this type of memory, the bits of data are stored in slowly discharging capacitors). The current sun6i/sun8i DRAM size detection logic, which is inherited from the Allwinner code, relies on using a large magic signature with the hope that it is unique enough and unlikely to ever accidentally match this leftover garbage data in RAM. But this approach is inherently unsafe, as can be demonstrated using the following test program: /***** A testcase for reproducing the problem ******/ void main(int argc, char *argv[]) { size_t size, i; uint32_t *buf; /* Allocate the buffer */ if (argc < 2 || !(size = (size_t)atoi(argv[1]) * 1048576) || !(buf = malloc(size))) { printf("Need buffer size in MiB as a cmdline argument\n"); exit(1); } /* Fill it with the Allwinner DRAM "magic" values */ for (i = 0; i < size / 4; i++) buf[i] = 0xaa55aa55 + ((uintptr_t)&buf[i] / 4) % 64; /* Try to reboot */ system("reboot"); /* And wait */ for (;;) {} } /***************************************************/ If this test program is run on the device (giving it a large chunk of memory), then the DRAM size detection logic in u-boot gets confused after reboot and fails to initialize DRAM properly. A better approach is not to rely on luck and abstain from making any assumptions about the properties of the leftover garbage data in RAM. Instead just use a more reliable code for testing whether two different addresses refer to the same memory location. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sun8i: Add dram initialization supportHans de Goede2015-01-14-1/+349
| | | | | | | | | | | | | | | | Based on the register / dram_para headers from the Allwinner u-boot / linux sources + the init sequences from boot0. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Fill memory before comparing it when doing dram init on sun6iHans de Goede2015-01-14-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sun8i boot0 code fills the DRAM with a "random" pattern before comparing it at different offsets to do columns, etc. detection. The sun6i boot0 code does not do it, instead relying on the memory contents being random enough to begin with for the memcmp to properly detect the wrap-around address, iow it is working purely by chance. Since our sun6i dram code was modelled after the boot0 code it contained the same issue. This commit fixes this by filling the memory with a unique, distinct pattern. The new mctl_mem_fill function this introduces is added as an inline helper in dram.h, so that it can be shared with the sun8i dram code. While at it move mctl_mem_matches to dram.h for re-use in sun8i too. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Move await_completion dram helper to dram.hHans de Goede2015-01-14-37/+11
| | | | | | | | | | | | | | | | | | The await_completion helper is already copy pasted between the sun4i and sun6i dram code, and we need it for sun8i too, so lets make it an inline helper in dram.h, rather then adding yet another copy. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sun6i: clock_set_pll5: Calculate k and m rather then hardcoding themHans de Goede2015-01-14-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Our old hardcoded k and m values are based on PLL5 being configured in steps of 48 MHz, which is correct for sun6i where the DRAM PLL runs at twice the DRAM CLK, which is usually configured in 24 MHz step. But on the A23 (sun8i) the PLL5 runs at half the DRAM CLK, so we require 12 MHz steps. This commit adjusts clock_set_pll5 to automatically select the best k and m depending on the requested clk rate. Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sun6i: Add a sigma_delta_enable paramter to clock_set_pll5()Hans de Goede2015-01-14-3/+8
| | | | | | | | | | | | | | | | The sun8i dram code sometimes wants to enable sigma delta mode, add a parameter to allow this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: axp221: Add axp223 supportHans de Goede2015-01-14-1/+1
| | | | | | | | | | | | | | | | | | The axp223 appears to be the same as the axp221, except that it uses the rsb to communicate rather then the p2wi. At least all the registers we use are 100% the same. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Add support for the rsb (Reduced Serial Bus)Hans de Goede2015-01-14-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | sun8i (A23) introduces a new bus for communicating with the pmic, the rsb, the rsb is also used to communicate with the pmic on the A80, and is documented in the A80 user manual. This commit adds support for this based on the rsb driver from the allwinner u-boot sources. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sun6i: s/SUNXI_*P2WI*/SUN6I_*P2WI*/Hans de Goede2015-01-14-7/+7
| | | | | | | | | | | | | | | | The p2wi interface is only available on sun6i, adjust the gpio pinmux and base address defines for it to reflect this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Align PSCI stack calculation to commentJan Kiszka2015-01-14-1/+1
| | | | | | | | | | | | | | | | 0x400 is true 1K. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Add sunxi_get_sid helper functionHans de Goede2015-01-14-0/+19
| | | | | | | | | | | | | | | | | | | | On sun6i the SID is stored in the pmic, rather then in the SoC itself, add a helper function to abstract this away. This makes our MAC address generation code also work on sun6i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sun6i: dram: Do not try to initialize a second dram chan on A31sHans de Goede2015-01-14-7/+15
| | | | | | | | | | | | | | | | The A31s only has one dram channel, so do not bother with trying to initialize a second channel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sun6i: Add sunxi_get_ss_bonding_id() functionHans de Goede2015-01-14-1/+37
| | | | | | | | | | | | | | | | Add a sunxi_get_ss_bonding_id() function, and use it to differentiate between the A31s and the A31. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sun6i: Make dram clk and zq value Kconfig optionsHans de Goede2015-01-14-7/+5
|/ | | | | | | | | | | | It turns out that there is a too large spread between boards to handle this with a default value, turn this into Kconfig options, and set the values the factory images are using for the Colombus and Mele_M9 boards. Note this changes the ZQ default when not overriden through defconfig from 120 to 123, as that is what most boards seem to actually use. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: UniPhier: add UART initialization routine for low-level debugMasahiro Yamada2015-01-08-0/+104
| | | | | | | | | | | The low-level debugging functions are useful to debug the early boot stage where the full UART driver is not available. UniPhier SoCs need to initialize the UART port 0 to use this feature. The initialization routine is called at the very entry of the lowlevel_init(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: enable output of system busMasahiro Yamada2015-01-08-0/+14
| | | | | | | | For NAND boot on PH1-LD4, PH1-sLD8, and some other SoCs, the output of the system bus is disabled by default. It must be enabled by software to have access to the system bus. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: fix SRAM size on support cardMasahiro Yamada2015-01-08-3/+3
| | | | | | | | | | The max size of available memories on slot0 and slot1 is 32MB because - EA[25] signal is not output on the save-pin mode which is used PH1-LD4 or later SoCs. - EA[25] signal is not connected by the limitation (or bug?) of the PLD logic of DCC support card. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* keystone: set default pci mode to root complexKaricheri, Muralidharan2015-01-05-0/+33
| | | | | | | pci ports are used as root complex in Linux. So set this as default in u-boot for keystone devices Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
* arm: omap: reset sata on bootDmitry Lifshitz2015-01-05-0/+9
| | | | | | | | | | | | | On OMAP platforms (like OMAP5) Linux kernel fails to detect a SATA device if it is used by U-Boot. It happens because U-Boot does not reset SATA controller before boot. Reset the controller on OS boot so that Linux will have a clean state to work with. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: Tom Rini <trini@ti.com>
* OMAP5+: sata/scsi: implement scsi_bus_reset()Dmitry Lifshitz2015-01-05-0/+6
| | | | | | | | Implement missing scsi_bus_reset() for SCSI subsystem commands on OMAP platforms. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: Tom Rini <trini@ti.com>
* Revert "ARM: omap4: Update sdram setting for panda rev A6"Nishanth Menon2015-01-05-4/+0
| | | | | | This reverts commit 47a4bea6af77b01d59a410d09a4c34b2dd14cf50. Signed-off-by: Nishanth Menon <nm@ti.com>
* omap-common/hwinit-common.c: timer_init() doesn't need to touch gdTom Rini2015-01-05-5/+0
| | | | | | | | | | The gd will be cleared at first so we don't need to set arch.tbl to 0. In addition, the checks later against lastinc also work fine with an initial value of 0 here. This also brings us in line with sunxi code for example. Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* am33xx: Drop timer_init call from s_initTom Rini2015-01-05-1/+0
| | | | | | | | In both SPL and non-SPL cases we will make a call to timer_init() early on and do not need to call it again within s_init(). Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* socfpga: Drop redundant save_boot_paramsTom Rini2015-01-05-7/+0
| | | | | | | | | | | | The save_boot_params function here is the same as the default weak one from arch/arm/cpu/armv7/start.S, drop. Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Marek Vasut <marex@denx.de>
* ARM: bootm: do not add PSCI to fdt when booting in secure mode.Ian Campbell2015-01-05-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 8bc347e2ec17 "ARM: bootm: Allow booting in secure mode on hyp capable systems" added the capability to select nonsec vs sec mode boot via an environment var. There is a subtle gotcha with this functionality, which is that the PSCI nodes are still created in the fdt (via armv7_update_dt->fdt_psci) even when booting in secure mode. Which means that if the kernel is PSCI aware then it will fail to boot because it will try and do PSCI from secure world, which won't work. This likely didn't get noticed before because the original purpose was to support booting the legacy linux-sunxi kernels which don't understand PSCI. To fix expose boot_nonsec (renaming with armv7_ prefix) outside of bootm.c and use from the virt-dt code. As well as avoiding the creation of the PSCI nodes we should also avoid reserving the secure RAM, so do so. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-02-0/+50
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| * arm:mx6sx add QSPI supportPeng Fan2014-12-31-0/+50
| | | | | | | | | | | | | | Add QSPI support for mx6solox. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-30-1/+11
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| * | arm: socfpga: Change watchdog timeoutStefan Roese2014-12-21-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current current watchdog timeout of 12 seconds is a bit small for booting into Linux, especially when using a NFS based rootfs. So lets change this timeout to a more defensive value of 30 seconds. Also we now call the hw_watchdog_init() function so that we override the value already configured from the Preloader. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-30-1/+2
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| * \ \ Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2014-12-30-0/+49
| |\ \ \ | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | | imx:mx6 fix return value of mxc_get_clockPeng Fan2014-12-19-1/+2
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mxc_get_clock's return type is unsigned int. 'return -1' is same with 'return 0xffffffff', so 0 should be used as the return value when unsupported mxc_clock type is passed to mxc_get_clock. Also include an err message when unsupported mxc_clock type is passed to mxc_get_clock. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2014-12-30-3/+654
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| * | | | ARM: UniPhier: display boot swap pin status by pinmon commandMasahiro Yamada2014-12-30-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This information would be useful enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: add dump command of DDR PHY parametersMasahiro Yamada2014-12-30-0/+237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a dump command of DDR PHY parameters of UniPhier SoC family. It might not be used very often for the regular operation but it would be useful when something goes wrong with DDR memories. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: UniPhier: add DDR PHY training codeMasahiro Yamada2014-12-30-3/+414
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | This training code provides run-time adjustment of DDR PHY parameters for stable DDR operation. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2014-12-30-0/+6
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| * | | arm: exynos: clock: support SPLL as mmc source clock for exynos5420Joonyoung Shim2014-12-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MMC of exynos5420 can select SPLL as source clock, so add to support SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Odroid-XU3: Add support for Odroid-XU3Hyungwon Hwang2014-12-22-0/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for Odroid-XU3. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | bcm281xx: add support for "USB OTG clock"Steve Rae2014-12-29-0/+49
|/ / | | | | | | | | | | | | | | enable this clock with the following: clk_usb_otg_enable((void *)HSOTG_BASE_ADDR) Signed-off-by: Steve Rae <srae@broadcom.com> Reviewed-by: Felipe Balbi <balbi@ti.com>
generated by cgit v1.1 at 2024-12-26 18:41:39 +0000