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* imx: mx6: ddr add dram io configuration and header file for i.MX6SLPeng Fan2015-09-02-0/+55
| | | | | | | | | Define two structure mx6sl_iomux_ddr_regs and mx6sl_iomux_grp_regs. Add a new function mx6sl_dram_iocfg to configure dram io. Add header file to define macros for register address. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6: ddr correct tRFC and tXSPeng Fan2015-09-02-2/+2
| | | | | | | | | | | To Chip density 4Gb, tRFC should be 300ns, see "Table 61 — Refresh parameters by device density" of JESD79-3E. tXS(min) is max(5nCK, tRFC(min) + 10ns). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx6: ddr no support MMDC1 for i.MX6SLPeng Fan2015-09-02-2/+4
| | | | | | | | | i.MX 6SoloLite only supports MMDC0, so do not access MMDC1 for i.MX 6SL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* tbs2910: use full name in Kconfig board selectionSoeren Moch2015-09-02-1/+1
| | | | Signed-off-by: Soeren Moch <smoch@web.de>
* imx: clock support enet2 anatop clock supportPeng Fan2015-09-02-5/+18
| | | | | | | | | | | | | | | | To i.MX6SX/UL, two ethernet interfaces are supported. Add ENET2 clock support: 1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed. To value 1, only i.MX6SX/UL can pass the check. 2. Modify board code who use this api to follow new api prototype. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
* imx: mx6 move TARGET_xx Kconfig option to mx6 specific Kconfig filePeng Fan2015-09-02-2/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move TARGET_xx Kconfig option based on mx6 to arch/arm/cpu/armv7/mx6/Kconfig. Add enable "CONFIG_ARCH_MX6" for boards based on mx6. Then we can choose target boards using "make ARCH=arm menuconfig" with ARCH_MX6 defined. If using original way, we have no chance to enable ARCH_MX6 when "make menuconfig". Even define CONFIG_ARCH_MX6=y in xx_defconfig, kconfig will complains "arch/../configs/platinum_titanium_defconfig:3: warning: override: TARGET_PLATINUM_TITANIUM changes choice state" Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Eric Bénard <eric@eukrea.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Marek Vasut <marex@denx.de> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Soeren Moch <smoch@web.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Soeren Moch <smoch@web.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
* sunxi: Enable non-secure access to RTC on sun6i (A31s)Chen-Yu Tsai2015-08-31-0/+24
| | | | | | | | | | | | | | On the A31s the RTC is by default secured. Thus when u-boot loads the kernel in non-secure world, the RTC is unavailable. The SoC has a TrustZone Protection Controller, which can be used to enable non-secure access to the RTC. On the A31 the TZPC doesn't seem to do anything, i.e. changes to its register contents do not affect access to the RTC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: OMAP5/AM43xx: remove enabling USB clocks from enable_basic_clocks()Kishon Vijay Abraham I2015-08-28-42/+0
| | | | | | | | | | Now that we have separate function to enable USB clocks, remove enabling USB clocks from enable_basic_clocks(). Now board_usb_init() should take care to invoke enable_usb_clocks() for enabling USB clocks. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: AM43xx: Add functions to enable and disable USB clocksKishon Vijay Abraham I2015-08-28-0/+70
| | | | | | | | | | | Added functions to enable and disable USB clocks which can be invoked during USB init and USB exit respectively. Cc: Roger Quadros <rogerq@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5: Add functions to enable and disable USB clocksKishon Vijay Abraham I2015-08-28-0/+97
| | | | | | | | | | | Added functions to enable and disable USB clocks which can be invoked during USB init and USB exit respectively. Cc: Roger Quadros <rogerq@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2Kishon Vijay Abraham I2015-08-28-0/+18
| | | | | | | | Enabled clocks for the second dwc3 controller and second USB PHY present in DRA7. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap-common: SYS_BOOT fallback logic correction and support for more devicesPaul Kocialkowski2015-08-28-10/+22
| | | | | | | | | | | | | | | | | | | | | The SYS_BOOT-based fallback shouldn't only check for one of the conditions of use and then let the switch/case handle each boot device without enforcing the conditions for each type of boot device again. For instance, this behaviour would trigger the fallback for UART when BOOT_DEVICE_UART is defined, CONFIG_SPL_YMODEM_SUPPORT is enabled (which should be a show-stopper) and e.g. BOOT_DEVICE_USB is enabled and not CONFIG_SPL_USB_SUPPORT. Separating the logic for USB and UART solves this. In addition, this adds support for more peripheral devices (USBETH and CPGMAC) to the fallback mechanism. Note that the USBETH boot device should always be different from the USB boot device (each should match a different bootrom handoff case). Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Hannes Schmelzer <oe5hpm@oevsv.at> Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
* ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0Nishanth Menon2015-08-28-0/+9
| | | | | | | | | | | | | | | | | | | DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work. Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform. NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Add detection of ES2.0Nishanth Menon2015-08-28-0/+9
| | | | | | | | | | | | | | | | | Add support for detection of ES2.0 version of DRA7 family of processors. ES2.0 is an incremental revision with various fixes including the following: - reset logic fixes - few assymetric aging logic fixes - MMC clock rate fixes - Ethernet speed fixes - edma fixes for mcasp [ravibabu@ti.com: posted internal for an older bootloader] Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROLMasahiro Yamada2015-08-18-2/+0
| | | | | | | | | | | | | | | | | | | As we discussed a couple of times, negative CONFIG options make our life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ... and here is another one. Now, there are three boards enabling OF_CONTROL on SPL: - socfpga_arria5_defconfig - socfpga_cyclone5_defconfig - socfpga_socrates_defconfig This commit adds CONFIG_SPL_OF_CONTROL for them and deletes CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert the logic. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-08-18-0/+186
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| * ARM: AM43XX: Add functions to enable and disable EDMA3 clocksVignesh R2015-08-17-0/+36
| | | | | | | | | | | | | | | | | | Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: OMAP5: Add functions to enable and disable EDMA3 clocksVignesh R2015-08-17-0/+45
| | | | | | | | | | | | | | | | | | Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: OMAP5: Add support for disabling clocks in ubootKishon Vijay Abraham I2015-08-17-0/+53
| | | | | | | | | | | | | | | | | | Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: AM43xx: Add support for disabling clocks in ubootKishon Vijay Abraham I2015-08-17-0/+52
| | | | | | | | | | | | | | | | | | Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | ARM: exynos: move SoC sources to mach-exynosThomas Abraham2015-08-17-8018/+0
|/ | | | | | | | | | | | | | Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow reuse of existing code for ARMv8 based Exynos platforms. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* sun6i: clock: Add support for the mipi pllHans de Goede2015-08-14-0/+55
| | | | | | | | Add support for the mipi pll, this is necessary for getting higher dotclocks with lcd panels. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: clock: Add clock_get_pll3() helper functionHans de Goede2015-08-14-0/+21
| | | | | | | Add a helper function to get the pll3 clock rate. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: SPL: Use CONFIG_SPL_DM not CONFIG_DMTom Rini2015-08-12-1/+1
| | | | | | | | | We now have the CONFIG_SPL_DM for code within SPL to toggle caring about DM or not. Without this change platforms that do enable CONFIG_DM but not CONFIG_SPL_DM may be broken (such as OMAP5). Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@konsulko.com>
* gpio: omap: Drop 'method' parameterTom Rini2015-08-12-32/+34
| | | | | | | | | | The "method" parameter was part of the original port of the driver from the kernel. At some point this may have been added to allow for future differentiation (as omap1 and omap2 have different GPIO IP blocks, so this wasn't an unreasonable thing to do). At this point however it's just extra overhead, so drop. Signed-off-by: Tom Rini <trini@konsulko.com>
* am33xx: Update DT files, add am335x_gp_evm_config targetTom Rini2015-08-12-30/+6
| | | | | | | | | | - Re-sync DT files for am33xx with Linux Kernel v4.1 - Include DT file now for the "AM335x GP EVM" and build target for it, via device tree and DM. - We only need to provide platform data for UART when OF_CONTROL isn't also enabled really. We can just push GPIO to coming from DT Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: am43xx: enable spi clockNikita Kiryanov2015-08-12-0/+1
| | | | | | | | | | Add spi clock to the list of am43xx basic clocks to make the SPI subsystem available on am43xx systems. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Jagan Teki <jteki@openedev.com>
* ARM: DRA72: disable workaround for 801819Nishanth Menon2015-08-12-0/+11
| | | | | | | | | | | | | | | | | DRA72x processor variants are single core and it does not export ACP[1]. Hence, we have no source for generating an external snoop requests which appear to be key to the deadlock in DRA72x design. Since we build the same image for DRA74x and DRA72x platforms, lets runtime detect and disable the workaround (in favor of performance) on DRA72x platforms. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: DRA7/ OMAP5: implement Auxiliary Control Register configurationNishanth Menon2015-08-12-0/+6
| | | | | | | | | | Implement logic for ACR(Auxiliary Control Register) configuration using ROM Code smc service. Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: Introduce erratum workaround for 801819Nishanth Menon2015-08-12-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add workaround for Cortex-A15 ARM erratum 801819 which says in summary that "A livelock can occur in the L2 cache arbitration that might prevent a snoop from completing. Under certain conditions this can cause the system to deadlock. " Recommended workaround is as follows: Do both of the following: 1) Do not use the write-back no-allocate memory type. 2) Do not issue write-back cacheable stores at any time when the cache is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it is implementation defined whether cacheable stores update the cache when the cache is disabled it is not expected that any portable code will execute cacheable stores when the cache is disabled. For implementations of Cortex-A15 configured without the “L2 arbitration register slice” option (typically one or two core systems), you must also do the following: 3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111 So, we provide an option to disable write streaming on OMAP5 and DRA7. It is a rare condition to occur and may be enabled selectively based on platform acceptance of risk. Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3] is set to 0. Note: certain unicore SoCs *might* not have REVIDR[3] not set, but might not meet the condition for the erratum to occur when they donot have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency Extensions). Such SoCs will need the work around handled in the SoC specific manner, since there is no ARM generic manner to detect such configurations. Based on ARM errata Document revision 18.0 (22 Nov 2013) Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: cache: implement a default weak flush_cache() functionWu, Josh2015-08-12-13/+0
| | | | | | | | | | | | | | | | | Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: Josh Wu <josh.wu@atmel.com>
* ARM: cache: add an empty stub function for invalidate/flush dcacheWu, Josh2015-08-12-8/+0
| | | | | | | | | | | | | Since some driver like ohci, lcd used dcache functions. But some ARM cpu don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all ARM cpu in arch/arm/lib/cache.c. And ARM cpu still can implemnt its own cache functions on the cpu folder. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: York Sun <yorksun@freescale.com>
* LG Optimus Black (P970) codename sniper supportPaul Kocialkowski2015-08-12-0/+8
| | | | | | | | | | | | | | | | | | | | The LG Optimus Black (P970) codename sniper is a smartphone that was designed and manufactured by LG Electronics (LGE) and released back in 2011. It is using an OMAP3630 SoC GP version, which allows running U-Boot and the U-Boot SPL from the ground up. This port is aimed at running an Android version such as Replicant, the fully free Android distribution. However, support for upstream Linux with device-tree and common GNU/Linux distros boot commands could be added in the future. For more information about the journey to freeing this device, please read the series of blog posts at: http://code.paulk.fr/article20/a-hacker-s-journey-freeing-a-phone-from-the-ground-up-first-part Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Add CONFIG_OF_SUPPORT] Signed-off-by: Tom Rini <trini@konsulko.com>
* omap3: Reboot mode supportPaul Kocialkowski2015-08-12-0/+38
| | | | | | | | | | | | | | Reboot mode is written in scratchpad memory before reboot in the form of a single char, that is the first letter of the reboot mode string as passed to the reboot function. This mechanism is supported on OMAP3 both my the upstream kernel and by various TI kernels. It is up to each board to make use of this mechanism or not. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* sunxi: usb-phy: Never power off the usb portsHans de Goede2015-08-08-0/+7
| | | | | | | | | | | | | | | | | | | | | USB devices are not really designed to get the power bounced off and on at them. Esp. USB powered harddisks do not like this. Currently we power off the USB ports both on a "usb reset" and when booting the kernel, causing the usb-power to bounce off and then back on again. This patch removes the powering off calls, fixing the undesirable power bouncing. Note this requires some special handling for the OTG port: 1) We must skip the external vbus check if we've already enabled our own vbus to avoid false positives 2) If on an usb reset we no longer detect that the id-pin is grounded, turn off vbus as that means an external vbus may be present now Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* exynos: Add support for springSimon Glass2015-08-05-0/+6
| | | | | | | | | | Spring is the first ARM-based HP Chromebook 11. It is similar to snow and it uses the same Samsung Exynos5250 chip. But has some unusual features. Mainline support for it has lagged snow (both in kernel and U-Boot). Now that the exynos5 code is common we can support spring just by adding a device tree and a few lines of configuration. Signed-off-by: Simon Glass <sjg@chromium.org>
* exynos: Tidy up CPU frequency displaySimon Glass2015-08-05-5/+2
| | | | | | | | | | | | | Line up the display with the line below, e.g.: CPU: Exynos5250 @ 1.7 GHz Model: Google Spring DRAM: 2 GiB MMC: EXYNOS DWMMC: 0 Also show the speed as GHz where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org>
* exynos: Add support for the DisplayPort hotplug detectSimon Glass2015-08-05-0/+10
| | | | | | Allow this function to be selected using the pinmux API. Signed-off-by: Simon Glass <sjg@chromium.org>
* exynos: Enable the debug UART in SPLSimon Glass2015-08-05-0/+5
| | | | | | | | As a debugging aid, allow UART3 to be used as a debug UART in SPL. This is a precursor to proper UART support, which requires a substantial refactor. Signed-off-by: Simon Glass <sjg@chromium.org>
* usb: musb-new: CONFIG_MUSB prefix replacement with CONFIG_USB_MUSBPaul Kocialkowski2015-08-05-1/+1
| | | | | | | | | USB-related options are usually prefixed with CONFIG_USB and platform-specific adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* armv7/ls102xa: Fix non-boot cpus cannot correctly fall in spin tableWang Dongsheng2015-08-03-0/+8
| | | | | | | | | | | Bootrom will put cpus into WFE state when boot cpu release cpus, so target cpu cannot correctly go to spin state. Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target cpu can fall into u-boot spin table. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-08-02-110/+376
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| * imx:mx6ul add dram spl configuration and header filePeng Fan2015-08-02-10/+51
| | | | | | | | | | | | | | | | | | | | | | | | 1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs. 2. Add a new function mx6ul_dram_iocfg to configure dram io. 3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support runtime check, but not hardcoding #ifdef macros. 4. Introduce mx6ul-ddr.h, which includes the register address for DRAM IO configuration. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6ul update soc related settingsPeng Fan2015-08-02-5/+4
| | | | | | | | | | | | | | | | 1.Update WDOG settings. 2.No need to gate/ungate all PFDs for i.MX6UL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * imx: mx6ul select SYS_L2CACHE_OFFPeng Fan2015-08-02-0/+4
| | | | | | | | | | | | | | | | | | i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6 chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled. There is on specific switch for on/off L2 Cache, so default select SYS_L2CACHE_OFF. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx:mx6ul add clock supportPeng Fan2015-08-02-59/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add enet, uart, i2c, ipg clock support for i.MX6UL. 2. Correct get_periph_clk, it should account for MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK. 3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function, but not use 'ifdef'. 4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX. 5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q) || defined....", only need one CONFIG_PCIE_IMX in header file. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * arm: mx6: kconfig: don't select CPU_V7 per boardNikita Kiryanov2015-08-02-3/+0
| | | | | | | | | | | | | | | | | | | | CPU_V7 is already selected by ARCH_MX6, so no point in selecting it again by boards that depend on ARCH_MX6. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| * arm: mx6: cm-fx6: move cm-fx6 target under ARCH_MX6Nikita Kiryanov2015-08-02-0/+8
| | | | | | | | | | | | | | | | | | | | cm-fx6 is an MX6 based board, and the menuconfig hierarchy should reflect that. Make TARGET_CM_FX6 dependant on ARCH_MX6. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * imx: mx6qp Enable PRG clock for IPUPeng Fan2015-08-02-0/+5
| | | | | | | | | | | | | | | | | | | | The i.MX6DQP has a PRG module, need to enable its clock for using IPU. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Brown Oliver <B37094@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: mx6: hab : Remove the cache issue workaroud in hab for i.MX6QPYe.Li2015-08-02-1/+2
| | | | | | | | | | | | | | | | | | Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
generated by cgit v1.1 at 2024-10-07 22:28:00 +0000