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* ARM: omap: fix GPMC address-map size for NAND and NOR devicespekon gupta2014-07-25-2/+7
| | | | | | | | | | | | | | | | | | | | | | Fixes commit a0a37183bd75e74608bc78c8d0e2a34454f95a91 ARM: omap: merge GPMC initialization code for all platform 1) NAND device are not directly memory-mapped to CPU address-space, they are indirectly accessed via following GPMC registers: - GPMC_NAND_COMMAND_x - GPMC_NAND_ADDRESS_x - GPMC_NAND_DATA_x Therefore from CPU's point of view, NAND address-map can be limited to just above register addresses. But GPMC chip-select address-map can be configured in granularity of 16MB only. So this patch uses GPMC_SIZE_16M for all NAND devices. 2) NOR device are directly memory-mapped to CPU address-space, so its address-map size depends on actual addressable region in NOR FLASH device. So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map size configuration. Signed-off-by: Pekon Gupta <pekon@ti.com>
* ARM: OMAP: Fix handling of errata i727Rajendra Nayak2014-07-25-1/+2
| | | | | | | | | | | | The errata is applicable on all OMAP4 (4430 and 4460/4470) and OMAP5 ES 1.0 devices. The current revision check erroneously implements this on all DRA7 varients and with DRA722 device (which has only 1 EMIF instance) infact causes an asynchronous abort and ends up masking it in CPSR, only to be uncovered once the kernel switches to userspace. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: spl: add K2E SoC supportKhoronzhuk, Ivan2014-07-25-0/+8
| | | | | | | | Keystone2 K2E SoC has slightly different spl pll settings then K2HK, so correct this. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: keystone2: add MSMC cache coherency support for K2E SOCHao Zhang2014-07-25-7/+9
| | | | | | | | | | This patch adds Keystone2 K2E SOC specific code to support MSMC cache coherency. Also create header file for msmc to hold its API. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: keystone2: clock: add K2E clock supportHao Zhang2014-07-25-5/+130
| | | | | | | | This patch adds clock definitions and commands to support Keystone2 K2E SOC. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: keystone: clock: move K2HK SoC dependent code in separate fileKhoronzhuk, Ivan2014-07-25-124/+138
| | | | | | | | | | This patch in general spit SoC type clock dependent code and general clock code. Before adding keystone II Edison k2e SoC which has slightly different dpll set, move k2hk dependent clock code to separate clock-k2hk.c file. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* k2hk: use common KS2_ prefix for all hardware definitionsKhoronzhuk, Ivan2014-07-25-20/+20
| | | | | | | | | | | | | | | | Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and add KS2_ prefix where it's needed. It requires to change names also in places where they're used. Align lines and remove redundant definitions in kardware-k2hk.h at the same time. Using common KS2_ prefix helps resolve redundant redefinitions and adds opportunity to use KS2_ definition across a project not thinking about what SoC should be used. It's more convenient and we don't need to worry about the SoC type in common files, hardware.h will think about that. The hardware.h decides definitions of what SoC to use. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* keystone2: add possibility to turn off all dspsHao Zhang2014-07-25-0/+59
| | | | | | | | | | By default all DSPs are turned off, for another case option to turn off them is added in this commit. Also add command to turn off itself. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* keystone2: move cpu_to_bus() to keystone.cHao Zhang2014-07-25-0/+29
| | | | | | | | | The SoC related common functions in board.c should be placed to a common keystone.c arch file. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: keystone2: keystone_nav: make it dependent on keystone driverKhoronzhuk, Ivan2014-07-25-1/+1
| | | | | | | | | | | This driver is needed in case if keystone driver is used. Currently only keystone_net driver uses it. So to avoid redundant code compilation make the keystone_nav dependent on keystone net driver. It also leads to compilation errors for boards that does't use it. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* keystone2: ddr: add DDR3 PHY configs updated for PG 2.0Hao Zhang2014-07-25-0/+19
| | | | | | | | | Add DDR3 PHY configs updated for PG 2.0 Also add DDR3A PHY reset before init for PG2.0 SoCs. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* keystone: ddr3: add ddr3.h to hold ddr3 APIKhoronzhuk, Ivan2014-07-25-3/+3
| | | | | | | | It's convinient to hold ddr3 function definitions in separate file such as ddr3.h. So move this from hardware.h to ddr3.h. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: keystone2: psc: use common PSC baseKhoronzhuk, Ivan2014-07-25-23/+19
| | | | | | | | Use common keystone2 Power Sleep controller base address instead of directly deciding which keystone2 SoC is used in psc module. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: omap: Remove unused arch/arm/cpu/armv7/omap3/mem.cStefan Roese2014-07-25-139/+0
| | | | | | | | | | | | These functions have been merged into the common GPMC init code with this commit a0a37183 (ARM: omap: merge GPMC initialization code for all platform). The file is not compiled any more. So remove it as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Pekon Gupta <pekon@ti.com>
* ARM: omap: Fix GPMC init for OMAP3 platformsStefan Roese2014-07-25-1/+1
| | | | | | | | | | | | | | | | | | | Commit a0a37183 (ARM: omap: merge GPMC initialization code for all platform) broke NAND on OMAP3 based platforms. I noticed this while testing the latest 2014.07-rc version on the TAO3530 board. NAND detection did not work with this error message: NAND: nand: error: Unable to find NAND settings in GPMC Configuration - quitting As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC was not initialized for NAND at all. This patch now fixes this issue. Tested on TAO3530 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Pekon Gupta <pekon@ti.com>
* socfpga: Relocate arch common functions away from boardChin Liang See2014-07-05-0/+24
| | | | | | | | | | | | | To move the arch common function away from board folder to arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication for other non Altera dev kit which is using socfpga device. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Detlev Zundel <dzu@denx.de>
* socfpga: Adding Scan Manager driverChin Liang See2014-07-05-1/+214
| | | | | | | | | | | | Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* ARM: cache_v7: use __weakJeroen Hofstee2014-07-04-38/+7
| | | | | | | | | | This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added. cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Tom Rini <trini@ti.com>
* Merge remote-tracking branch 'u-boot-samsung/master'Albert ARIBAUD2014-07-01-98/+296
|\ | | | | | | | | | | | | | | Conflicts: boards.cfg Conflict was trivial between goni maintainer change and lager_nor removal.
| * Exynos5420: Let macros be used for exynos5420Akshay Saraswat2014-06-23-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Macros defined in exynos5_setup.h specific to SMDK5420 are required for Peach-Pit too. Hence, replacing CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these macros for all the boards based on Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: DMC: Add software read levelingAkshay Saraswat2014-06-13-5/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes Read DQ and DQS are not in phase. Since, this phase shift differs from board to board, we need to calibrate it at DRAM init phase, that's read DQ calibration. This patch adds SW Read DQ calibration routine to compensate this skew. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * DMC: exynos5420: Gate CLKM to when reading PHY_CON13Doug Anderson2014-06-13-5/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when CLKM is running. If we stop CLKM when sampling it the glitches all go away, so we'll do that as per Samsung suggestion. We also check the "is it locked" bits of PHY_CON13 and loop until they show the the value sampled actually represents a locked value. It doesn't appear that the glitching and "is it locked" are related, but it seems wise to wait until the PHY tells us the value is good before we use it. In practice we will not loop more than a couple times (and usually won't loop at all). Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: Remove code for enabling read levelingAkshay Saraswat2014-06-13-71/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch intends to remove all code which enables hardware read leveling. All characterization environments may not cope up with h/w read leveling enabled, so we must disable this. Also, disabling h/w read leveling improves the MIF LVcc value (LVcc value is the value at which DDR will fail to work properly). Improving LVcc means we have enough voltage margin for MIF. When h/w leveling is enabled, we have almost zero volatge margin. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_initAkshay Saraswat2014-06-13-13/+5
| | | | | | | | | | | | | | | | | | | | Passing fewer arguments is better and mem_iv_size is never used. Let's keep only one argument and make it cleaner. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Revert "exynos: Enable PSHOLD in SPL"Minkyu Kang2014-06-13-2/+0
| | | | | | | | This reverts commit eb0dd9986c3883820ff888c3738b013c0a7d918c.
* | Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-01-1/+1
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| * | tegra20: display: fix checking of return valueJeroen Hofstee2014-06-19-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | The calling code seems a bit in doubt about the return value of fdtdec_lookup_phandle. Since it returns a negative value on error (and fdt_node_offset_by_phandle as well), check for that. cc: Wei Ni <wni@nvidia.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-01-76/+7
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| * | OMAP: disable gpmc timeout safely for reenablingStefano Babic2014-06-19-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gpmc timeout is disabled and the reset counter is set to 0. However, if later a driver activates the timeout setting the reset to a valid value, the old reset value with zero is still valid for the first access. In fact, the timeout block loads the reset counter after a successful access. Found on a am335x board with a FPGA connected to the GPMC bus together with the NAND. When the FPGA driver in kernel activates the timeout, the system hangs at the first access by the NAND driver. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | omap3: board: trivial: add void for no argsJeroen Hofstee2014-06-19-2/+2
| | | | | | | | | | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| * | cpu: armv7: am33x: ddr: write emif ref_ctrl_shadow registerFelipe Balbi2014-06-19-0/+1
| | | | | | | | | | | | Signed-off-by: Felipe Balbi <balbi@ti.com>
| * | ARM: keystone: aemif: move aemif driver to drivers/memory/ti-aemif.cKhoronzhuk, Ivan2014-06-19-72/+0
| | | | | | | | | | | | | | | | | | | | | | | | Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | mtd: nand: davinci: add header file for driver definitionsKhoronzhuk, Ivan2014-06-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The definitions inside emif_defs.h concern davinci nand driver and should be in it's header. So create header file for davinci nand driver and move definitions from emif_defs.h and nand_defs.h to it. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> [trini: Fixup more davinci breakage] Signed-off-by: Tom Rini <trini@ti.com>
| * | omap: Don't enable GPMC CS0 with nothing attachedAsh Charles2014-06-19-1/+2
| |/ | | | | | | | | | | | | | | | | | | | | If CONFIG_(NAND|NOR|ONENAND) is not defined, no configuration is set for GPMC on chip select #0---size is 0. In this case, the GPMC configuration should be reset but not enabled. Enabling causes the Gumstix DuoVero board to hang when entering Linux. Signed-off-by: Ash Charles <ashcharles@gmail.com> [trini: Switch to testing base as GPMC_SIZE_256M is 0x0] Signed-off-by: Tom Rini <trini@ti.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-30-7/+557
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| * | imx: correct HAB status for new chip TOStefano Babic2014-06-17-7/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to: http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/log/?h=imx_v2009.08_3.0.35_4.1.0 ENGR00287268 mx6: fix the secure boot issue on the new tapout chip commit 424cb1a79e9f5ae4ede9350dfb5e10dc9680e90b newer i.MX6 silicon revisions have an updated ROM and HAB API table. Please see also: i.MX Applications Processors Documentation Engineering Bulletins EB803, i.MX 6Dual/6Quad Applications Processor Silicon Revsion 1.2 to 1.3 Comparison With this change the secure boot status is correctly displayed Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | mx6: add mmdc configuration for MX6Q/MX6DLTim Harvey2014-06-06-0/+491
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add function for configuring iomux based on board-specific regs - add function for configuring mmdc based on board-specific and chip-specific data Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | | Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'Albert ARIBAUD2014-06-25-0/+1
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| * | | arm: zynq: fix a bug in Zynq linker scriptMasahiro Yamada2014-06-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 41623c91 moved exception handlers to ".vectores" section but it missed to adjust Zynq linker script. Zynq boards hang up after relocation because "_start" symbol does not point to the correct address and gd->relocaddr gets insane. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Michal Simek <monstr@monstr.eu> Tested-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-25-60/+62
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| * | | cosmetic: Whitespace fixVasili Galka2014-06-11-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Vasili Galka <vvv444@gmail.com>
| * | | am33xx/omap: Allow cache enable for all Sitara/OMAPSimon Glass2014-06-11-58/+60
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | Enable the cache for all devices, unless CONFIG_SYS_DCACHE_OFF is defined. This speeds up the Beaglebone Black boot considerable. (Tested only on Beaglebone Black with SD card boot) Signed-off-by: Simon Glass <sjg@chromium.org>
* | | ARMv7: at91: enable ICache and DCache.Wu, Josh2014-06-14-0/+2
|/ / | | | | | | | | | | | | | | | | | | | | For at91 armv7 SoC (SAMA5D3x), only LCD and macb used DMA. Now as the lcd and macb driver already support dcache. So we can enable dcache now. Also we can enable icache without any problem. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | arm:am33xx: Add a scale_vcores() hookTom Rini2014-06-06-0/+11
| | | | | | | | | | | | | | Similar to OMAP4/5 we need to scale the voltage up prior to changing the clock frequencies up higher. Add a similar hook to start with. Signed-off-by: Tom Rini <trini@ti.com>
* | ARM: AM43xx: Fix UART clocks enablingLokesh Vutla2014-06-06-0/+9
| | | | | | | | | | | | | | | | | | | | After enabling a module, SW has to wait on IDLEST bit until it is Fully functional. This wait is missing for UART module and there is a immediate access of UART registers after this. So there is a chance of hang on this module( This can happen when we are running from MPU SRAM). So waiting for IDLEST bit. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | keystone: init: enable UART1 to be able use it from kernelMurali Karicheri2014-06-06-0/+9
| | | | | | | | | | | | | | | | | | | | Currently PWREMU_MGMT is not configured in the Linux generic UART driver as this register seems to be specific TI UART IP. So this needs to be enabled in u-boot to use UART1 from kernel space. Acked-By: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | arm:am33xx: Rework s_init and add board_early_init_fTom Rini2014-06-06-2/+14
| | | | | | | | | | | | | | | | | | | | | | With the changes to the i2c framework (and adopting the omap24xx_i2c driver to them) we can no longer call i2c functions prior to gd having been set and cleared. When SPL booting, this is handled by setting gd to point to SRAM in s_init. However in the cases where we are loaded directly by ROM (memory mapped NOR or QSPI) we need to make use of the normal hooks to slightly delay these calls. Signed-off-by: Tom Rini <trini@ti.com>
* | arm:am33xx: Make dram_init call sdram_init() in some contextsTom Rini2014-06-06-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have two contexts for booting these platforms. One is SPL which is roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main, board_init_f from SPL, ... then U-Boot loads. The other is a memory-mapped XIP case (NOR or QSPI) where we do not run an SPL. In this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init, _main, regular board_init_f. In the first case s_init will set a valid gd and then be able to call sdram_init which in many cases will need i2c (which needs a valid gd for gd->cur_i2c_bus). In this second case we must (and are able to and should) defer sdram_init() into dram_init() called by board_init_f as gd will have been set in _main and cleared in board_init_f. Signed-off-by: Tom Rini <trini@ti.com>
* | am43xx_evm: Add qspiboot targetSourav Poddar2014-06-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The ePOS EVM and EVM SK have QSPI as an option to boot. Add a qspiboot target that utilizes QSPI for env and so forth as an example of best practices. As QSPI is booted from directly we need to chang CONFIG_SYS_TEXT_BASE. Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices we need to handle that elsewhere, once NAND support is also added. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* | omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and ↵pekon gupta2014-06-06-12/+0
| | | | | | | | | | | | | | | | | | | | | | GPMC_NAND_ECC_LP_x16_LAYOUT OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros to configure GPMC controller for x7 or x8 bit device connected to its interface. Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above macros can be completely removed. Signed-off-by: Pekon Gupta <pekon@ti.com>