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* OMAP3 SPL: Rework memory initalization and devkit8000 supportTom Rini2011-12-06-13/+15
| | | | | | | | | This changes to making the board be responsible for providing the memory initialization timings in SPL and converts the devkit8000 to this framework. In SPL we try and initialize both CS0 and CS1. Cc: Frederik Kriewitz <frederik@kriewitz.eu> Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Change mem_ok to clear again after reading backTom Rini2011-12-06-0/+1
| | | | | | | | It's possible to need to call this function on the same banks multiple times so we want to be sure that 'pos A' is cleared out again at the end. Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Add a helper function to set timings in SDRCTom Rini2011-12-06-55/+61
| | | | | | | | Since we go through the sequence to setup the SDRC timings more than once, break this logic out into its own function and have that function call mem_ok() to make sure the memory is usable. Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Update SDRC dram_init to always call make_cs1_contiguous()Tom Rini2011-12-06-12/+11
| | | | | | | | | | | | | We update the comment in make_cs1_contiguous() to be a little bit more clear (it's been copy/pasted from other silicons) and then explain in dram_init() why we need to always try this. Note that in the previous behavior we were always calling this on boards that never had cs1 populated anyhow so making sure we do this always is fine and will correct things like omap3evm detecting an invalid amount of memory (384MB). Signed-off-by: Tom Rini <trini@ti.com>
* omap3: mem: Comment enable_gpmc_cs_config moreTom Rini2011-12-06-3/+9
| | | | | | | Expand the "enable the config" comment to explain what the bit shifts are and define out two of the magic numbers. Signed-off-by: Tom Rini <trini@ti.com>
* AM35xx: add EMAC supportIlya Yanok2011-12-06-0/+45
| | | | | | AM35xx has DaVinci-compatible EMAC. Signed-off-by: Ilya Yanok <yanok@emcraft.com>
* omap4: fix IO settingAneesh V2011-12-06-1/+6
| | | | | | | | | | | | The value from TRIM is not working for some 4430 silicons. So, override with hw team recommended value. However, for 4460 TRIM value shall be used as long as the part is trimmed This fixes boot problem on some OMAP4430 ES2.0 Panda boards out there. Cc: Steve Sakoman <sakoman@gmail.com> Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4460: add ES1.1 identificationAneesh V2011-12-06-1/+9
| | | | Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4: emif: fix error in driverAneesh V2011-12-06-2/+2
| | | | | | | | | | There was a typo in the EMIF driver. It went un-noticed because it affected only when automatic detection is enabled and even then half the memory was configured and identified properly. Reported-by: Rockefeller <rockefeller.lin@innocomm.com> Signed-off-by: Aneesh V <aneesh@ti.com>
* omap: remove I2C from SPLAneesh V2011-12-06-1/+0
| | | | | | | Due to some recent changes I2C is no longer required in SPL. Remove the i2c_init() call to save some space Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4460: fix TPS initializationAneesh V2011-12-06-8/+0
| | | | | | | | | | | TPS power IC is controlled using a GPIO (gpio_wk7). This GPIO should be maintained at logic 1 always. As such an internal pull-up on this pin will do the job, driving the GPIO outuput is not needed. This will avoid the need of using GPIO library in SPL and also may save some power. Signed-off-by: Aneesh V <aneesh@ti.com>
* start.S: remove omap3 specific code from start.SAneesh V2011-12-06-23/+8
| | | | | | | Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com> Acked-by: Tom Rini <trini@ti.com>
* armv7: setup vectorAneesh V2011-12-06-0/+17
| | | | | | | | The vector is not correctly setup in armv7 except for OMAP3. Correcting this. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: include armv7/cpu.c in SPL buildAneesh V2011-12-06-2/+2
| | | | | | | | | This allows SPL to have default implementation of save_boot_params(), useful for SoCs that do not intend to override this default implementation Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: disable L2 cache in cleanup_before_linux()Aneesh V2011-12-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | We were not disabling external caches before jumping to kernel. We were flushing all caches including external caches and disabling caches globally in CP15 System Control register. Apparently this is not enough. The bootstrap loader in Linux kernel that does decompression enables data-caches again, flush them after use and disable them before jumping to kernel proper. However, it's not aware of the external caches. Since we have left external cache enabled, external cache will get used once caches are enabled globally, but it's not flushed because decompressor is not aware of external caches. When it jumps to kernel with caches disabled globally, we have stale data in the external cache and a coherency problem. This was breaking the boot for OMAP4 with latest mainline kernel. The solution is to disable external caches in cleanup_before_linux(). With this fix kernel is booting again. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com>
* OMAP3: Use sdelay from arch/arm/cpu/armv7/syslib.c instead of cloning that.Alexander Holler2011-11-29-11/+1
| | | | | | | | There is no need to have such a function twice. Signed-off-by: Alexander Holler <holler@ahsoftware.de> Acked-by: Dirk Behme <dirk.behme@googlemail.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* arch/arm/cpu/armv7/s5p-common/pwm.c: fix GCC 4.6 warningAnatolij Gustschin2011-11-16-2/+0
| | | | | | | | | Fix: pwm.c: In function 'pwm_config': pwm.c:85:16: warning: variable 'timer_rate_hz' set but not used [-Wunused-but-set-variable] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* omap4/5: Add support for booting with CH.Sricharan2011-11-15-41/+164
| | | | | | | | | | | | | | | | Configuration header(CH) is 512 byte header attached to an OMAP boot image that will help ROM code to initialize clocks, SDRAM etc and copy U-Boot directly into SDRAM. CH can help us in by-passing SPL and directly boot U-boot, hence it's an alternative for SPL. However, we intend to support both CH and SPL for OMAP4/5. Initialization done through CH is limited and is not equivalent to that done by SPL. So U-Boot has to distinguish between the two cases and handle them accordingly. This patch takes care of doing this. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap5: emif: Add emif/ddr configurations required for omap5 evmSricharan2011-11-15-213/+514
| | | | | | | | | | | | | Add the emif configurations required for omap5 soc.Add the correct ddr part configurations required for omap5 evm board. EDB8164B3PH from ELPIDA is the part used on the board. Also changes are done to retain some part of the code common for OMAP4/5 and keep only the remaining in the Soc specific directories. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap5: clocks: Add clocks support for omap5 platform.Sricharan2011-11-15-470/+991
| | | | | | | | | | | | Adding the correct configurations required for dplls, clocks, for omap5 Soc. Also changes are done to retain some part of the code common for OMAP4/5 and move only the remaining to the Soc specific directories. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap5: Add minimal support for omap5430.Sricharan2011-11-15-319/+362
| | | | | | | | | | | | | | | | This patch adds the minimal support for OMAP5. The platform and machine specific headers and sources updated for OMAP5430. OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Also moved some part of code from the basic platform support that can be made common for OMAP4/5. Rest is kept out seperately. The same approach is followed for clocks and emif support in the subsequent patches. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: make omap4 code common for future reuseSricharan2011-11-15-9/+16
| | | | | | | | | Much of omap4 soc support code can be reused for omap5. Move them to the omap-common directory to facilitate this. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* mx53: Turn off child clocks before reconfigure perclk_rootFabio Estevam2011-11-04-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | In addition to ensuring that PERCLK remains at least 2.5 times slower than the AHB clock, certain steps need to be followed to ensure robust operation of PERCLK when reconfiguring the PERCLK clock source. To properly configure the PERCLK clock source, the following steps are required: 1.In the CCGR registers, gate the clocks to all PERCLK-dependent modules. 2.Select the desired input clock for the PERCLK root clock (to be either source from the peripherals main source clock or the lp_apm clock source). Refer to the CMCBR register, perclk_lp_apm_sel bit. 3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers to the desired setting. Refer to the CBCDR register for details. 4.In the CCGR registers, enable the desired clocks for the PERCLK-dependent module clocks. If these steps aren't followed, GPT timer may stop and the kernel stops at "Calibrating delay loop". Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* omap/spl: actually enable the consoleIlya Yanok2011-11-03-0/+2
| | | | | | | | | Currently OMAP SPL code does all the initialization but does not set the gd->have_console value so no output is actually performed. This patch sets gd->have_console to 1. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* Reduce build timesWolfgang Denk2011-11-03-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot Makefiles contain a number of tests for compiler features etc. which so far are executed again and again. On some architectures (especially ARM) this results in a large number of calls to gcc. This patch makes sure to run such tests only once, thus largely reducing the number of "execve" system calls. Example: number of "execve" system calls for building the "P2020DS" (Power Architecture) and "qong" (ARM) boards, measured as: -> strace -f -e trace=execve -o /tmp/foo ./MAKEALL <board> -> grep execve /tmp/foo | wc -l Before: After: Reduction: ================================== P2020DS 20555 15205 -26% qong 31692 14490 -54% As a result, built times are significantly reduced, typically by 30...50%. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Albert Aribaud <albert.aribaud@free.fr> cc: Graeme Russ <graeme.russ@gmail.com> cc: Mike Frysinger <vapier@gentoo.org> Tested-by: Graeme Russ <graeme.russ@gmail.com> Tested-by: Matthias Weisser <weisserm@arcor.de> Tested-by: Sanjeev Premi <premi@ti.com> Tested-by: Simon Glass <sjg@chromium.org> Tested-by: Macpaul Lin <macpaul@gmail.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2011-10-28-41/+2491
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: ARM: Add Calxeda Highbank platform dkb: make mmc command as default enabled Marvell: dkb: add mmc support ARM: pantheon: add mmc definition davinci: remove config.mk file from the sources ARM:AM33XX: Add support for TI AM335X EVM ARM:AM33XX: Added timer support ARM:AM33XX: Add emif/ddr support ARM:AM33XX: Add clock definitions ARM:AM33XX: Added support for AM33xx omap3/emif4: fix registers definition davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM davinci: emac: add support for more than 1 PHYs davinci: emac: add new features to autonegotiate for EMAC da850evm: Move LPSC configuration to board_early_init_f() omap4_panda: Build in cmd_gpio support on panda omap: Don't use gpio_free to change direction to input mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset OMAP3: overo : Add environment variable optargs to bootargs OMAP3: overo: Move ethernet CS4 configuration to execute based on board id OMAP3: overo : Use ttyO2 instead of ttyS2. da830: add support for NAND boot mode dm36x: revert cache disable patch dm644X: revert cache disable patch devkit8000: Add malloc space omap: spl: fix build break due to changes in FAT OMAP3 SPL: Provide weak omap_rev_string omap: beagle: Use ubifs instead of jffs2 for nand boot omap: overo: Disable pull-ups on camera PCLK, HS and VS signals omap: overo: Configure mux for gpio10 SPL: Add DMA library omap3: Add interface for omap3 DMA omap3: Add DMA register accessors omap3: Add Base register for DMA arm, davinci: add missing LSPC define for MMC/SD1 U-Boot/SPL: omap4: Make ddr pre-calculated timings as default. DaVinci: correct MDSTAT.STATE mask omap4: splitting padconfs into common, 4430 and 4460 omap4: adding revision detection for 4460 ES1.1 omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL gplug: fixed build error as a result of code cleanup patch kirkwood_spi: add dummy spi_init() gpio: mvmfp: reduce include platform file ARM: orion5x: reduce dependence of including platform file serial: reduce include platform file for marvell chip ARM: kirkwood: reduce dependence of including platform file ARM: armada100: reduce dependence of including platform file ARM: pantheon: reduce dependence of including platform file Armada100: Add env storage support for Marvell gplugD Armada100: Add SPI flash support for Marvell gplugD Armada100: Add SPI support for Marvell gplugD SPI: Add SPI driver support for Marvell Armada100 dreamplug: initial board support. imx: fix coding style misc: pmic: drop old Freescale's pmic driver MX31: mx31pdk: use new pmic driver MX31: mx31ads: use new pmic driver MX31: mx31_litekit: use new pmic driver MX5: mx53evk: use new pmic driver MX5: mx51evk: use new pmic driver MX35: mx35pdk: use new pmic driver misc: pmic: addI2C support to pmic_fsl driver misc: pmic: use I2C_SET_BUS in pmic I2C MX5: efikamx/efikasb: use new pmic driver MX3: qong: use new pmic driver RTC: Switch mc13783 to generic pmic code MX5: vision2: use new pmic driver misc: pmic: Freescale PMIC switches to generic PMIC driver misc:pmic:samsung Enable PMIC driver at GONI target misc:pmic:max8998 MAX8998 support at a new PMIC driver. misc:pmic:core New generic PMIC driver mx31pdk: Remove unneeded config mx31: provide readable WEIM CS accessor MX51: vision2: Set global macros I2C: Add i2c_get/set_speed() to mxc_i2c.c ARM: Update mach-types devkit8000: Add config to enable SPL MMC boot devkit8000: protect board_mmc_init arm, post: add missing post_time_ms for arm cosmetic, post: Codingstyle cleanup arm, logbuffer: make it compileclean tegra2: Enable MMC for Seaboard tegra2: Add more pinmux functions tegra2: Rename PIN_ to PINGRP_ tegra2: Add more clock functions tegra2: Clean up board code a little tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
| * ARM: Add Calxeda Highbank platformRob Herring2011-10-27-0/+169
| | | | | | | | | | | | | | | | | | Add basic support for Calxeda Highbank platform. Only minimal support with serial and SATA are included. Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * ARM:AM33XX: Add support for TI AM335X EVMChandan Nath2011-10-27-1/+67
| | | | | | | | | | | | | | | | | | This patch adds basic support for booting the board. This patch adds support for the UART necessary to get to the u-boot prompt. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * ARM:AM33XX: Added timer supportChandan Nath2011-10-27-0/+2
| | | | | | | | | | | | | | This patch adds timer support for AM33xx platform. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * ARM:AM33XX: Add emif/ddr supportChandan Nath2011-10-27-0/+351
| | | | | | | | | | | | | | | | This patch adds AM33xx emif/ddr support along with board specific defines. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * ARM:AM33XX: Add clock definitionsChandan Nath2011-10-27-0/+274
| | | | | | | | | | | | | | This patch adds basic clock definition of am33xx SoC. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * ARM:AM33XX: Added support for AM33xxChandan Nath2011-10-27-0/+246
| | | | | | | | | | | | | | | | This patch adds basic support for AM33xx which is based on ARMV7 Cortex A8 CPU. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * omap: Don't use gpio_free to change direction to inputJoe Hershberger2011-10-27-7/+0
| | | | | | | | | | | | | | | | | | gpio_free() should not have the side effect of setting the line to input since this prevents the gpio command from being able to set a line as output. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * omap: spl: fix build break due to changes in FATAneesh V2011-10-27-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | FAT library now uses malloc() and free(). But SPL doesn't have heap until now. Setup a heap in SDRAM to fix this issue. However this increases SPL footprint beyond the available SRAM budget. So, compile out some fancy features in the SDARM init bring back footprint under control CC: Sandeep Paulraj <s-paulraj@ti.com> CC: Wolfgang Denk <wd@denx.de> Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * OMAP3 SPL: Provide weak omap_rev_stringTom Rini2011-10-27-6/+8
| | | | | | | | | | | | | | | | | | We add an weak version of omap_rev_string in omap-common/spl.c and while at it drop the omap3 version. Move the prototype over to <asm/omap_common.h> with the other SPL functions. Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * omap4: splitting padconfs into common, 4430 and 4460Ricardo Salveti de Araujo2011-10-27-2/+11
| | | | | | | | | | | | | | | | | | | | Not all padconfs are the same between 4430 and 4460, so instead of working around this with an if, we should have an specific padconf structure for both chips (like handling the differences between the LEDs GPIOs and TPS). Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@linaro.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * omap4: adding revision detection for 4460 ES1.1Ricardo Salveti de Araujo2011-10-27-1/+11
| | | | | | | | | | | | | | Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@linaro.org> 2 files changed, 17 insertions(+), 1 deletions(-) Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROLRicardo Salveti de Araujo2011-10-27-3/+3
| | | | | | | | | | | | | | | | OMAP4460 has a different set of values for the ID code, so moving the old ones to be related just with 4430. Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@linaro.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * imx: fix coding styleFabio Estevam2011-10-27-8/+2
| | | | | | | | | | | | | | | | | | Fix checkpatch warning and errors in several i.MX related files. While at it also address a checkpatch warning at arch/arm/cpu/armv7/mx5/soc.c regarding the usage of extern in a C file. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * tegra2: Add more pinmux functionsSimon Glass2011-10-27-1/+521
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for changing pinmux functions of pin groups. This is done by defining a PMUX_FUNC_... enum which can be used to select the function for each group using pinmux_set_func(). It is also possible to enable pullup/pulldown, and the existing tristate functionality is retained. Also provided is a means of configuring a list of pingroups by providing a configuration table to pinmux_config_table(). Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
| * tegra2: Rename PIN_ to PINGRP_Simon Glass2011-10-27-3/+3
| | | | | | | | | | | | | | | | | | | | | | The pin groupings are better named PINGRP, since on Tegra2 they refer to multiple pins. Sorry about this, but better to get it right now when there is only a small amount of code affected. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
| * tegra2: Add more clock functionsSimon Glass2011-10-27-7/+817
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds most of the clock functions required by board and driver code: -query and adjust peripheral clocks -query and adjust PLLs -reset and enable control These functions are plumbed in as required. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
| * tegra2: Rename CLOCK_PLL_ID to CLOCK_IDSimon Glass2011-10-27-4/+4
| | | | | | | | | | | | | | | | | | | | | | Rename CLOCK_PLL_ID to CLOCK_ID which takes account of the fact that the code now deals with both PLL clocks and source clocks. This also tidied up the assert() to match the one sent upstream, and fixes an error in the PWM id. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
* | GCC4.6: Squash warnings in omap4 clocks.cMarek Vasut2011-10-27-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | clocks.c:606:2: warning: format '%08x' expects type 'unsigned int', but argument 2 has type 'u32 * const' clocks.c:633:2: warning: format '%08x' expects type 'unsigned int', but argument 2 has type 'u32 * const' Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org>
* | GCC4.6: Squash warning in tegra2 board.cMarek Vasut2011-10-27-1/+1
|/ | | | | | | | | | board.c:43:2: warning: format '%08lX' expects type 'long unsigned int', but argument 2 has type 'u32' Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org>
* build: add missing $(AR)->$(cmd_link_o_target) updateMike Frysinger2011-10-22-1/+1
| | | | | | | | | Seems people fixed their files to use libfoo.o, but didn't actually update the creation targets to use $(cmd_link_o_target). Update the rest of the Makefile's found with grep. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Tested-by: Simon Glass <sjg@chromium.org>
* Move timestamp and version files into 'generated' subdirSimon Glass2011-10-17-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a rather subtle build problem where the build time stamp is not updated for out-of-tree builds if there exists an in-tree build which has a valid timestamp file. So if you do an in-tree build, then an out-of-tree build your timestamp will not change. The correct timestamp_autogenerated.h lives in the object tree, but it is not always found there. The source still lives in the source tree and when compiling version.h, it includes timestamp_autogenerated.h. Since the current directory is always searched first, this will come from the source tree rather than the object tree if it exists there. This affects dependency generation also, which means that common/cmd_version.o will not even be rebuilt if you have ever done an in-tree build. A similar problem exists with the version file. This change moves both files into the 'generated' subdir, which is already used for asm-offsets.h. Then timestamp.h and version.h are updated to include the files from there. There are other places where these generated files are included, but I cannot see why these don't just use the timestamp.h and version.h headers. So this change also tidies that up. I have tested this with in- and out-of-tree builds, but not SPL. I have looked at various other options for fixing this, including sed on the dep files, -I- and -include flags to gcc, but I don't think they can be made to work. Comments welcome. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* MX5: Clean up the output of "clocks" commandMarek Vasut2011-09-30-7/+9
| | | | | | | | | | | | | | | | The new output looks like this: > clocks PLL1 800 MHz PLL2 665 MHz PLL3 216 MHz AHB 133000 kHz IPG 66500 kHz IPG PERCLK 665000 kHz Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org>
* MX5: Add AHB clock reporting and fix IPG clock reportingMarek Vasut2011-09-30-9/+27
| | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Liu <jason.hui@linaro.org> Acked-by: Jason Liu <jason.hui@linaro.org>
* MX5: Modify the PLL decoding algorithmMarek Vasut2011-09-30-10/+56
| | | | | | | | | | The PLL decoding algorithm didn't take into account many configuration bits. Adjust it according to Linux kernel. Also, add PLL4 for MX53. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Hui <jason.hui@linaro.org> Tested-by: Jason Liu <Jason.hui@linaro.org>
generated by cgit v1.1 at 2024-09-12 21:12:54 +0000