| Commit message (Collapse) | Author | Age | Lines |
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On MX7D, boot rom can provide some boot information such as boot device,
arm freq, axi freq, etc. (see the structure below)
Offset Byte4 | Byte3 | Byte2 | Byte1
0x0 Reserved | Boot Device Type | Boot Device Instance | Reserved
0x4 ARM core frequency(in Hz)
0x8 AXI bus frequency(in Hz)
0x0C DDR frequency(in Hz)
0x10 GPT1 input clock frequency(in Hz)
0x14 Reserved
0x18
0x1C
The boot information can be accessed by get the pointer at 0x1E8. This patch
changes the u-boot to use the new approach. When manufacture boot, the info
recorded is the actual SD port, not the failed device.
Signed-off-by: Ye.Li <B37916@freescale.com>
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The iomuxc structure has changed to add 0x4000 offset for i.MX6SX and UL,
so when using this structure to access gpr registers needs to change
the base address to IOMUXC_BASE_ADDR.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Get the Unique ID of the chip from the fuse TESTER0 and TESTER1.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Change MXC_CCM_CCGR6_I2C4_xx to MXC_CCM_CCGR6_I2C4_SERIAL_xx
Remove duplicated mxs_set_vadcclk
Correct enable_pll_video usage
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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add i.MX6UL clock related settings/macros/apis
When using TFT43AB, its pixel size is 480x272 which needs a
slow pix clock. Without apply the test_div in PLL video, we can't
get the pix clock in the rate.
So change the LCDIF clock calculation to use the test_div.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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I2C4 support for i.MX
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Remove PCIe, xPU power, PL310 L2 Cache for MX6UL.
Update FEC MAC address, WDOG settings, USDHC clock rate.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Since the system counter driver will also be used by mx6ul, move
this timer driver to imx-common and rename it as syscounter.c
For mx6ul and mx7, configurations are used for choose the GPT timer
or system counter timer (default).
GPT timer: CONFIG_GPT_TIMER
System counter timer: CONFIG_SYSCOUNTER_TIMER
Signed-off-by: Ye.Li <B37916@freescale.com>
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Update settings for PRE. Value for Saturation THR of PREx,
changed from 0x20 to 0x10 to make system more stable.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 02e7090604e55d9690532294b02b499609d46e63)
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In i.MX7d platform, fec MDC root clock is ENET_AXI_ROOT_CLK, not
ipg clock, correct it.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit 07105e18dd0899c47ef80d3fddecf3ef250d895a)
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Merge hab_caam_clock_enable and hab_caam_clock_disable into
one function
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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This problem is found when debugging QuadSPI. When "A" bit is enabled,
unaligned access will cause data abort exception. Actually, we do not
want this exception. So clear the align bit for MX6 SOCs.
Tested this code with android team colleague and did not find problem.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit aa76a7e472e34bc59554f9932d611b1047d24590)
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Since the following piece settings can not be in DCD table, we
add them in enable_ipu_clock.
"
setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator
setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator
setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0
setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1
setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2
setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3
setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0
setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1
setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2
setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE
"
CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h,
the settings sure will effect.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 61cec88a59ebf450dd1352d81e03b5aa842e1d71)
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Use correct GPR address.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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This EPDC/EPXP QoS setting is needed for EPDC stress test to pass.
This patch remove the #ifdef to make sure set_epdc_qos be called always.
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit d2fb113740b2c67958862503dda2a40191ab0899)
(cherry picked from commit 581aa86581bb1178c5df4ad5298e5b85c53f1186)
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Under very rare timing circumstances, transitioning into streaming
mode might create a data corruption. Present on Two or more processors
or 1 core with ACP, all revisions. This erratum can be worked round
by setting bit[22] of the undocumented Diagnostic Control Register to 1.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit 70ad44e523680de67dd8b7a7505d7f27799980ee)
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Incorrect hab_rvt addresses were used for getting HAB functions.
Need to change to addresses in unified section.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 5ae1cb9d8e7cd7babd1d7ef7f2303664a4e15c26)
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Apply errata based on PL310 version instead of compile
time. Also set Prefetch offset to 15, since it improves
memcpy performance by 35%. Don't enable Incr double
Linefill enable since it adversely affects memcpy
performance by about 32MB/s and reads by 90MB/s. Tested
with 4K to 16MB sized src and dst aligned buffer.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit 31751fa9cf29ef4056f49fe06a54700a89c9bdc5)
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To support lower clock frequency, needs to set post divider and
test divider in PLL_VIDEO. So update LCDIF clock settings function
to support this feature.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit b4d3b2a8eaf1ad1dc529ae2348d1646a2833b701)
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Ungate the EPDC clock at system up if the EPDC is enabled
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit f215632cb25d1076ab5c5465efdfad2212010d8d)
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Add the QoS settings function which is used for EPDC
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 725a3bbbe0a172a0f4619d99bc198b9367b9fc5d)
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The i.MX6QP has a PRG module, need to enable its clock for using
IPU.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Brown Oliver <B37094@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 089f399ea07db79d6bca8fdc08b442b59eb55feb)
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Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround
for i.MX6QP.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 96e13b57ead3ed00c3a32c5373c7a2a876947f99)
Conflicts:
arch/arm/cpu/armv7/mx6/hab.c
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Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.
A new CONFIG_MX6QP is introduced here and is used for the CCM difference.
At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 5e4d1537ce9a476c8404126350f05d8976c5aa35)
Conflicts:
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/include/asm/arch-mx6/crm_regs.h
include/configs/mx6_common.h
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Since i.MX6DQP has fixed the L2 cache issue, enable the double line
fill feature to provide better performance.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit aa8a38edb67d4d1375d10bee9bf46557369fb5c4)
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Add new cpu type for i.MX6DQP and providing a dynamical
detecting function.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit ccf3b130d71cf3dd9a97d3bb424931bf6bd7e8c0)
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For APBH-DMA enabled case, we have to enable rawnand clock for mxs_dma_init.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 42f42939bbd8161ce283a6af326d0f313cc4c36c)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Update driver codes and registers define for MX7. Implement udc callback
function in MX7 arch.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit e55c4f7bf5a66b34c2d01c42bac667cb3789b0c1)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add udc and fastboot support
We did not use the upstream way.
Currently use CI_UDC and USB_GAGDET of upstream can make fastboot work,
but lack of flash operation, so we still use our way.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add thermal driver for mx7
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Change macro name to make driver support more platforms.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Modify Makefile to support MX7
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Enable SNVS clock in clock_init function as default enabled clock.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit df1e45b3098f737d68517c51032472d12fd87666)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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The default u-boot reset is a internal WDOG reset (warm reset on i.MX6) which
does not have power and DDR reset. So the peripherals and DDR may meet problem.
When using the internal WDOG reset on i.MX7D ARM2 boards,
we meets two DDR issues:
1. On 12x12 ARM2, sometimes the system may hang in DCD because the DDRC Operating Mode
does not become to normal.
2. On 19x19 ARM2, the reset always brings system to USB download because the
DDR3 turns to unstable.
On the i.MX7D ARM2 board, the WDOG_B signal connects to POR_B or PMIC_PWRON. This gives
a chance to use a stronger reset. So in this patch, we set the IOMUX for WDOG_B pin and
enable WDOG_B signal output in WDOG WCR register.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 1192501c1fcf3b266eb22639a6bc93ac7c03b367)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Implement the auxiliary core booting for Cortex M4 on i.MX7
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit c1c8ba37d87493c16ec1a12bc36d47f909e0e733)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add HAB files for secure boot and image athentication.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 2447bbcdd4ffcbdbd4ebed1b25e67ea753332d9d)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Generic timer is added to mx7d, so add support for this.
In uboot, only system counter is needed, the timer events are not needed.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 514a79581c6a46df445d69f1fcb2b3bff9584162)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Introduce a new cpu type MXC_CPU_MX7D and relevant functions for mx7d.
Implement the soc.c for various system level functions like:
temperature check, arch init, get mac fuse, boot mode get/apply, etc.
Additional, enable building imx common platform files for mx7d.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 47d65aa6bdd109fd9141b5a5d64ab9deeb9dd2b3)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
Makefile
arch/arm/cpu/armv7/Makefile
arch/arm/imx-common/cpu.c
arch/arm/include/asm/arch-imx/cpu.h
arch/arm/include/asm/imx-common/boot_mode.h
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Since a new CCM with clock root slice is introduced in mx7. Provide
several APIs for configuring root slice in clock_slice.c
Implement clock/PLL relevant functions for modules in mx7d to
enable/disable/set/get clocks or PLLs.
From mx7d, the clocks are initialized in function "void clock_init(void)",
such as UART, USDHC, ECSPI, USB, WDOG, WEIM. These module don't have clock
setting functions in driver and BSP, and assume the clock is setup before
entering into u-boot. Because default root clock is 24Mhz OSC, we have
to setup these default clocks.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 73b511503aef9675e58baadc0639d59c8395bcb4)
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Add get_boot_device function.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Update hab with imx_v2014.04
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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On mx6sx, the CCM register bits for GPMI are different as other
mx6 platforms. Modify the GPMI clock function to support mx6sx.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add mx6sx support for pcie power down
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Enable pcie support in uboot on imx6sx sd boards
- enable_pcie_clock should be call before ssp_en is set,
since that ssp_en control the phy_ref clk gate, turn on
it after the source of the pcie clks are stable.
- add debug info
- add rx_eq of gpr12 on imx6sx
- there are random link down issue on imx6sx. It's
pcie ep reset issue.
solution:reset ep, then retry link can fix it.
Signed-off-by: Richard Zhu <r65037@freescale.com>
(cherry picked from commit ec78595a24b5ff1020baa97b6d6e79a3a3326307)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/include/asm/arch-mx6/iomux.h
drivers/pci/pcie_imx.c
include/configs/mx6sxsabresd.h
Note:
There is an upstream patch 1b8ad74a6f8cea55a727dc4b399baac46d0daef1
to add support for mx6solox.
This patch is to add more stuff from our vendor imx_v2014.04 branch.
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As M4 is sourcing UART clk from OSC, to make UART work
when M4 is enabled, need to select OSC as clk parent,
24M OSC is enough for debug UART in uboot.
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 8b903f529370fdc59cc03b3ced954ed894753044)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add new function "arch_auxiliary_core_check_up" to check whether M4
is already up. Therefore, avoid starting M4 again when it is running.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 54a0803b29c5ab459bedfb2c68c1e94b89866aa1)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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When gis enable in uboot, the CSI0 input mux select setting
to vadc module, clean the bit when gis disabled.
Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit ae66b17b7da3be50dc81ca636b67e8e879f52e26)
(cherry picked from commit c83fd326e810c2fff44b8b02e78406d5d04c977c)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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The android boot needs get_board_serial function to get the
CPU uid as the serial number. Implement this function to read
the uid from fuse for all iMX6 platforms.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 8d355a9d6f138e1c1cd04dbadb7b5b3e2d692701)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Since the iMX6SL does not have PCIE module, should not define the
function "imx_set_pcie_phy_power_down" for it. Otherwise, get the
build warning below:
arch/arm/cpu/armv7/mx6/soc.c:446:13: warning: 'imx_set_pcie_phy_power_down'
defined but not used [-Wunused-function]
static void imx_set_pcie_phy_power_down(void)
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 987c48c07c9ef62fa3fe55faa6f7369b30637127)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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imx6sl doesn't have the pcie module, mask the pcie
related codes from imx6sl.
Signed-off-by: Richard Zhu <r65037@freescale.com>
(cherry picked from commit acaff11da33f8f0cb1521d3c48e64e7ed9a87bec)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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