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* arm: omap5: secure API for EMIF memory reservationsDaniel Allred2016-10-02-0/+127
| | | | | | | | | | | Create a few public APIs which rely on secure world ROM/HAL APIs for their implementation. These are intended to be used to reserve a portion of the EMIF memory and configure hardware firewalls around that region to prevent public code from manipulating or interfering with that memory. Signed-off-by: Daniel Allred <d-allred@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ti: omap5: Add Kconfig options for secure EMIF reservationsDaniel Allred2016-10-02-0/+26
| | | | | | | | | | | | | Adds start address and size config options for setting aside a portion of the EMIF memory space for usage by security software (like a secure OS/TEE). There are two sizes, a total size and a protected size. The region is divided into protected (secure) and unprotected (public) regions, that are contiguous and start at the start address given. If the start address is zero, the intention is that the region will be automatically placed at the end of the available external DRAM space. Signed-off-by: Daniel Allred <d-allred@ti.com>
* Convert CONFIG_SPL_SERIAL_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_POWER_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_NAND_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_MMC_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_LIBGENERIC_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_LIBDISK_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_LIBCOMMON_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_I2C_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_GPIO_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_FAT_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_EXT_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* ARM: OMAP5+: vcores: Drop unnecessary #ifndefsLokesh Vutla2016-08-20-0/+2
| | | | | | | | | | gpio_en field is introduced to detect if pmic is controlled by GPIO. Make this field 0 on all TPS659* pmics available on DRA7/OMAP5 based platforms and remove the #ifndefs. Reviewed-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* treewide: move CONFIG_PHYS_64BIT to KconfigMasahiro Yamada2016-08-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so that it is always available to the build system. Otherwise we can run into cases where we have inconsistent sizes of certain attributes. Ravi Babu reported offset mismatch of struct dwc3 across files since commit 95ebc253e6d4 ("types.h: move and redefine resource_size_t"). Since the commit, resource_addr_t points to phys_addr_t, whose size is dependent on CONFIG_PHYS_64BIT for ARM architecture. I tried my best to use "select" where possible (for example, ARMv8 architecture) because I think this kind of option is generally user- unconfigurable. However, I see some of PowerPC boards have 36BIT defconfigs as well as 32BIT ones. I moved CONFIG_PHYS_64BIT to the defconfigs for such boards. CONFIG_36BIT is no longer referenced, so all of the defines were removed from CONFIG_SYS_EXTRA_OPTIONS. Fixes: 95ebc253e6d4 ("types.h: move and redefine resource_size_t") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Ravi Babu <ravibabu@ti.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARM: dra7xx: Change DPLL_PER_HS13 divider valueLokesh Vutla2016-07-30-1/+1
| | | | | | | | | | | According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz clock, so that driver can use the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* arm: omap5: fix build dependency for secure devicesAndreas Dannenberg2016-07-22-1/+1
| | | | | | | | | | | Commit 17c2987 introduces an undesired dependency on CONFIG_SPL_LOAD_FIT when building U-Boot for AM57xx and DRA7xx high-security (HS) devices that causes the build to break when that option is not active. Fix this issue by only building the u-boot_HS.img target when building U-Boot into an actual FIT image. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: omap5: add U-Boot FIT signing and SPL image post-processingAndreas Dannenberg2016-07-14-0/+3
| | | | | | | | | | | | | | | Modify the SPL build procedure for AM57xx and DRA7xx high-security (HS) device variants to create a secure u-boot_HS.img FIT blob that contains U-Boot and DTB artifacts signed with a TI-specific process based on the CONFIG_TI_SECURE_DEVICE config option and the externally-provided image signing tool. Also populate the corresponding FIT image post processing call to be performed during SPL runtime. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: am57xx: Rename TARGET_BEAGLE_X15 as TARGET_AM57XX_EVMLokesh Vutla2016-06-13-2/+2
| | | | | | | | | board/am57xx supports all boards based on am57xx. Rename the taget as TARGET_AM57XX_EVM. Fixes: 74cc8b097d9af ("board: ti: beagle_x15: Rename to indicate support for TI am57xx evms") Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* arm: dra7xx: Assign omap_vcores based on board typeKeerthy2016-06-12-78/+0
| | | | | | | | | | Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
* ARM: DRA7: Consolidate voltage macros across different SoCsAnna, Suman2016-06-02-10/+10
| | | | | | | | | | | | | The voltage values for each voltage domain at an OPP is identical across all the SoCs in the DRA7 family. The current code defines one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x macros. Consolidate both these sets into a single set. This is done so as to minimize the number of macros used when voltage values will be added for other OPPs as well. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7: Define common macros for efuse register offsetsAnna, Suman2016-06-02-10/+10
| | | | | | | | | | | | | | Define a set of common macros for the efuse register offsets (different for each OPP) that are used to get the AVS Class 0 voltage values and ABB configuration values. Assign these common macros to the register offsets for OPP_NOM by default for all voltage domains. These common macros can then be redefined properly to point to the OPP specific efuse register offset based on the desired OPP to program a specific voltage domain. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* dra7xx: Enable USB_PHY3 32KHz clockRoger Quadros2016-06-02-2/+13
| | | | | | | DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled for USB1 instance in Super-Speed. Signed-off-by: Roger Quadros <rogerq@ti.com>
* ARM: OMAP5+: Provide enable/disable_usb_clocks() for CONFIG_USB_XHCI_OMAPRoger Quadros2016-06-02-1/+1
| | | | | | | | | CONFIG_USB_XHCI_OMAP is enabled for host mode independent of CONFIG_USB_DWC3 which is meant for gadget mode only. We need enable/disbale_usb_clocks() for host mode as well so provide for it. Fixes: 09cc14f4bcbf ("ARM: AM43xx: Add functions to enable and disable USB clocks" Signed-off-by: Roger Quadros <rogerq@ti.com>
* ARM: omap5: add hooks for cpu/SoC fdt fixupsDaniel Allred2016-05-27-0/+185
| | | | | | | | | | | | | | | Adds an fdt.c file in that defines the ft_cpu_setup() function, which should be called from a board-specific ft_board_setup()). This ft_cpu_setup() will currently do nothing for non-secure (GP) devices but contains pertinent updates for booting on secure (HS) devices. Update the omap5 Makefile to include the fdt.c in the build. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Madan Srinivas <madans@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* spl: build: ti: add support for secure boot imagesDaniel Allred2016-05-27-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Updates the SPL build so that when CONFIG_TI_SECURE_DEVICE is in use (which it should be when building for secure parts), the TI secure development package is used to create a valid secure boot image. The u-boot SPL build processes is NOT aware of the details of creating the boot image - all of that information is encapsulated in the TI secure development package, which is available from TI. More info can be found in README.ti-secure Right now, two image types are generated, MLO and X-LOADER. The types are important, as certain boot modes implemented by the device's ROM boot loader require one or the other (they are not equivalent). The output filenames are u-boot-spl_HS_MLO and u-boot-spl_HS_X-LOADER. The u-boot-spl_HS_MLO image is also copied to a file named MLO, which is the name that the device ROM bootloader requires for loading from the FAT partition of an SD card (same as on non-secure devices). Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Madan Srinivas <madans@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Add ABB setup for all domainsNishanth Menon2016-04-25-0/+16
| | | | | | | | | | | | | ABB should be initialized for all required domains voltage domain for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units and has been hard to debug. This specifically is a concern with DRA7 generation of SoCs since other than VDD_MPU, all other domains are only permitted to setup the voltages to required OPP only at boot. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5: Enable ABB configuration for MM voltage domainNishanth Menon2016-04-25-0/+5
| | | | | | | | | | Since we setup the voltage and frequency for the MM domain, we *must* setup the ABB configuration needed for the domain as well. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structureNishanth Menon2016-04-25-0/+3
| | | | | | | | | | | ABB TX_DONE mask will vary depending on ABB module. For example, 3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain, DRA7 has it on all domains with the exception of CORE, RTC. Hence, move the txdone mask definition over to structure describing voltage domain. Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5/DRA7: Get rid of control_std_fuse_opp_vdd_mpu_2Nishanth Menon2016-04-25-2/+0
| | | | | | | | | | | | | This information is already available under vcores->volts.efuse.reg. There is no reason for duplicating the information since AVS Class 0 definitions are common for OMAP5 and DRA7 and defined with STD_FUSE_OPP_* macros. This allows a central location of defining the ABB and voltage definitions especially since they are reused. This also makes it simpler to prevent mistakes involved when changing the boot OPP for the device. Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5/DRA7: Expose do_set_iodelayNishanth Menon2016-03-27-2/+2
| | | | | | | | do_set_iodelay can now be used from board files based on needs of the platforms variation they have. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5/DRA7: Split iodelay functionality into sub stepsNishanth Menon2016-03-27-14/+50
| | | | | | | | | | | | | | | | Since many platforms may need different pad configuration required depending on variation of the platform with minor deltas, it is easier to maintain a sub step based approach to allow for pin mux and iodelay configuration which may depend on the platform variations and need to be done in IO isolation. While we retain the older __recalibrate_iodelay function which provides a ready sequencing, __recalibrate_iodelay_start and __recalibrate_iodelay_end may be alternatively used now and the callers will be responsible for the correct sequencing of operations. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA72: sdram: Update sdram ext phy configuration for SR2.0Nishanth Menon2016-03-27-1/+43
| | | | | | | Based on data from EMIF configuration tool 1.1.1. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: hwdata: Update ioreg data for DRA72 SR2.0Nishanth Menon2016-03-27-1/+15
| | | | | | | | | Based on data from EMIF configuration tool 1.1.1. Expected update for CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT in the next revision of the tool has been incorporated as well. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA72x: Add support for detection of SR2.0Ravi Babu2016-03-27-0/+7
| | | | | | | | | Add support for detection of SR2.0 version of DRA72x family of processors. Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Move emif settings to board specific filesLokesh Vutla2016-03-14-147/+2
| | | | | | | | | | The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7: Enable EEPROM supportLokesh Vutla2016-03-14-0/+1
| | | | | | | | Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7: emif: Check for enable bits before updating leveling outputLokesh Vutla2016-03-14-8/+26
| | | | | | | | | Read and write leveling can be enabled independently. Check for these enable bits before updating the read and write leveling output values. This will allow to use the combination of software and hardware leveling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: ti: AM57xx: Add detection logic for AM57xx-evmKipisz, Steven2016-03-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current AM57xx evm supports both BeagleBoard-X15 (http://beagleboard.org/x15) and AM57xx EVM (http://www.ti.com/tool/tmdxevm5728). The AM572x EValuation Module(EVM) provides an affordable platform to quickly start evaluation of Sitara. ARM Cortex-A15 AM57x Processors (AM5728, AM5726, AM5718, AM5716) and accelerate development for HMI, machine vision, networking, medical imaging and many other industrial applications. This EVM is based on the same BeagleBoard-X15 Chassis and adds mPCIe, mSATA, LCD, touchscreen, Camera, push button and TI's wlink8 offering. Since the EEPROM contents are compatible between the BeagleBoard-X15 and the AM57xx-evm, we add support for the detection logic to enable support for various user programmable scripting capability. NOTE: U-boot configuration is currently a superset of AM57xx evm and BeagleBoard-X15 and no additional configuration tweaking is needed. This change also sets up the stage for future support of TI AM57xx EVMs to the same base bootloader build. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: ti: beagle_x15: Rename to indicate support for TI am57xx evmsKipisz, Steven2015-11-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BeagleBoard X15 (http://beagleboard.org/x15) support in u-boot does actually support two different platform configuration offered by TI. In addition to BeagleBoard X15, it also supports the TMDXEVM5728 (or more commonly known as AM5728-evm). Information about the TI AM57xx EVM can be found here http://www.ti.com/tool/tmdxevm5728 The EVM configuration is 1-1 compatible with BeagleBoard X15 with the additional support for mPCIe, mSATA, LCD, touchscreen, Camera, push button and TI's wlink8 offering. Hence, we rename the beagle_x15 directory to am57xx to support TI EVMs that use the AM57xx processor. By doing this we have common code reuse. This sets the stage to have a common u-boot image solution for multiple TI EVMs such as that already done for am335x and am437x. This sets the stage for upcoming multiple TI EVMs that share the same code base. NOTE: Commit eae7ae185335 ("am437x: Add am57xx_evm_defconfig using CONFIG_DM") introduced DT support for beagle_x15 under am57xx_evm platform name. However, this ignored the potential confusion arising for users as a result. To prevent this, existing beagle_x15_defconfig is renamed as am57xx_evm_nodt_defconfig to denote that this is the "non device tree" configuration for the same platform. We still retain am57xx-beagle-x15.dts at this point, since we just require the common minimum dts. As a result of this change, users should expect changes in build procedures('make am57xx_evm_nodt_defconfig' instead of 'make beagle_x15_defconfig'). Hopefully, this would be a one-time change. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
* omap5: omap_die_id supportPaul Kocialkowski2015-10-22-0/+12
| | | | | | | | This introduces omap5 support for omap_die_id, which matches the common omap_die_id definition. It replaces board-specific code to grab the die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5/AM43xx: remove enabling USB clocks from enable_basic_clocks()Kishon Vijay Abraham I2015-08-28-30/+0
| | | | | | | | | | Now that we have separate function to enable USB clocks, remove enabling USB clocks from enable_basic_clocks(). Now board_usb_init() should take care to invoke enable_usb_clocks() for enabling USB clocks. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5: Add functions to enable and disable USB clocksKishon Vijay Abraham I2015-08-28-0/+97
| | | | | | | | | | | Added functions to enable and disable USB clocks which can be invoked during USB init and USB exit respectively. Cc: Roger Quadros <rogerq@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2Kishon Vijay Abraham I2015-08-28-0/+18
| | | | | | | | Enabled clocks for the second dwc3 controller and second USB PHY present in DRA7. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0Nishanth Menon2015-08-28-0/+9
| | | | | | | | | | | | | | | | | | | DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work. Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform. NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Add detection of ES2.0Nishanth Menon2015-08-28-0/+9
| | | | | | | | | | | | | | | | | Add support for detection of ES2.0 version of DRA7 family of processors. ES2.0 is an incremental revision with various fixes including the following: - reset logic fixes - few assymetric aging logic fixes - MMC clock rate fixes - Ethernet speed fixes - edma fixes for mcasp [ravibabu@ti.com: posted internal for an older bootloader] Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5: Add functions to enable and disable EDMA3 clocksVignesh R2015-08-17-0/+45
| | | | | | | | | Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* gpio: omap: Drop 'method' parameterTom Rini2015-08-12-8/+10
| | | | | | | | | | The "method" parameter was part of the original port of the driver from the kernel. At some point this may have been added to allow for future differentiation (as omap1 and omap2 have different GPIO IP blocks, so this wasn't an unreasonable thing to do). At this point however it's just extra overhead, so drop. Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: DRA72: disable workaround for 801819Nishanth Menon2015-08-12-0/+11
| | | | | | | | | | | | | | | | | DRA72x processor variants are single core and it does not export ACP[1]. Hence, we have no source for generating an external snoop requests which appear to be key to the deadlock in DRA72x design. Since we build the same image for DRA74x and DRA72x platforms, lets runtime detect and disable the workaround (in favor of performance) on DRA72x platforms. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: DRA7/ OMAP5: implement Auxiliary Control Register configurationNishanth Menon2015-08-12-0/+6
| | | | | | | | | | Implement logic for ACR(Auxiliary Control Register) configuration using ROM Code smc service. Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
generated by cgit v1.1 at 2024-11-02 09:25:02 +0000