| Commit message (Collapse) | Author | Age | Lines |
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The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.
While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).
Signed-off-by: Stefan Agner <stefan@agner.ch>
(cherry picked from commit 8183b60202754d9d33ac1a2a68a5cc2cc4640fc6)
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The management data input/output (MDIO) requires open-drain,
i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
this feature. So to TO1.1, need to enable open drain by setting
bits GPR0[8:7] for TO1.1.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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This piece of code is for mx7, we should not use
do_mx6_showclocks.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time.
There are 26 peripherals impacted by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is set M4 to a different domain with A core.
So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only.
CM4 image will set the M4 to domain 1 only.
This patch enables the CONFIG_MXC_RDC for mx7d SABRESD board and ARM2 boards, and
setup the 26 IP resources to domain 0.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add the peripherals/masters definitions and registers base addresses
for mx7d RDC. Enable the RDC driver by setting CONFIG_MXC_RDC.
Signed-off-by: Ye.Li <B37916@freescale.com>
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enable fastboot command: "fastboot reboot-bootloader"
After type this command, the board will reboot to bootloader mode.
Set ANDROID_FASTBOOT_BOOT flag in SNVS_LPGPR before reboot.
Signed-off-by: Zhang Sanshan <b51434@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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1. Replace the UDC driver with community's USB gadget d_dnl driver.
2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and
EFI partitions are not support by i.MX.
3. Add FDT support to community's android image.
4. Change the booti command to boota, due to the booti has been used for
ARM64 image boot.
5. Modify boota implementation to load ramdisk and fdt to their loading
addresses specified in boot.img header, while bootm won't do it for
android image.
6. Modify the android image HAB implementation. Authenticate the boot.img
on the "load_addr" for both SD and NAND.
7. Enable new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot
with relevant header file "fsl_fastboot.h". While disabling the
configuration, the community fastboot is used.
8. Use community's way to combine cmdline in boot.img and u-boot environment,
not overwrite the cmdline in boot.img
Signed-off-by: Ye.Li <B37916@freescale.com>
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We should divide the 1000MHz ENET PLL clock by 10 in order to achieve
100MHz, so fix the divider accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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On mx7d 12x12 lpddr3 arm2 board, POR_B reset in uboot will fail stress
reset test, and hangs in rom code. Rom log buffer show thats wrong
hab_image_entry and runs into serial download mode. Also there is no
time delay reset circuit for this board.
We found when disable CONFIG_VIDEO, all seems fine. Actually,
only the following piece of code can make stress reset ok,
"
writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
while (--timeout) {
if (readl(®s->hw_lcdif_ctrl1) & LCDIF_CTRL1_VSYNC_EDGE_IRQ)
break;
udelay(1);
}
"
Here we use lcdif_power_down API which is better to shutdown lcdif same as
the way used in arch_preboot_os.
Implement reset_misc for mx7, since it does not hurt for others boards.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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On MX7D, boot rom can provide some boot information such as boot device,
arm freq, axi freq, etc. (see the structure below)
Offset Byte4 | Byte3 | Byte2 | Byte1
0x0 Reserved | Boot Device Type | Boot Device Instance | Reserved
0x4 ARM core frequency(in Hz)
0x8 AXI bus frequency(in Hz)
0x0C DDR frequency(in Hz)
0x10 GPT1 input clock frequency(in Hz)
0x14 Reserved
0x18
0x1C
The boot information can be accessed by get the pointer at 0x1E8. This patch
changes the u-boot to use the new approach. When manufacture boot, the info
recorded is the actual SD port, not the failed device.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Get the Unique ID of the chip from the fuse TESTER0 and TESTER1.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Since the system counter driver will also be used by mx6ul, move
this timer driver to imx-common and rename it as syscounter.c
For mx6ul and mx7, configurations are used for choose the GPT timer
or system counter timer (default).
GPT timer: CONFIG_GPT_TIMER
System counter timer: CONFIG_SYSCOUNTER_TIMER
Signed-off-by: Ye.Li <B37916@freescale.com>
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In i.MX7d platform, fec MDC root clock is ENET_AXI_ROOT_CLK, not
ipg clock, correct it.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit 07105e18dd0899c47ef80d3fddecf3ef250d895a)
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Merge hab_caam_clock_enable and hab_caam_clock_disable into
one function
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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This EPDC/EPXP QoS setting is needed for EPDC stress test to pass.
This patch remove the #ifdef to make sure set_epdc_qos be called always.
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit d2fb113740b2c67958862503dda2a40191ab0899)
(cherry picked from commit 581aa86581bb1178c5df4ad5298e5b85c53f1186)
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Incorrect hab_rvt addresses were used for getting HAB functions.
Need to change to addresses in unified section.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 5ae1cb9d8e7cd7babd1d7ef7f2303664a4e15c26)
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To support lower clock frequency, needs to set post divider and
test divider in PLL_VIDEO. So update LCDIF clock settings function
to support this feature.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit b4d3b2a8eaf1ad1dc529ae2348d1646a2833b701)
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Ungate the EPDC clock at system up if the EPDC is enabled
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit f215632cb25d1076ab5c5465efdfad2212010d8d)
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Add the QoS settings function which is used for EPDC
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 725a3bbbe0a172a0f4619d99bc198b9367b9fc5d)
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For APBH-DMA enabled case, we have to enable rawnand clock for mxs_dma_init.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 42f42939bbd8161ce283a6af326d0f313cc4c36c)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Update driver codes and registers define for MX7. Implement udc callback
function in MX7 arch.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit e55c4f7bf5a66b34c2d01c42bac667cb3789b0c1)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add thermal driver for mx7
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Enable SNVS clock in clock_init function as default enabled clock.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit df1e45b3098f737d68517c51032472d12fd87666)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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The default u-boot reset is a internal WDOG reset (warm reset on i.MX6) which
does not have power and DDR reset. So the peripherals and DDR may meet problem.
When using the internal WDOG reset on i.MX7D ARM2 boards,
we meets two DDR issues:
1. On 12x12 ARM2, sometimes the system may hang in DCD because the DDRC Operating Mode
does not become to normal.
2. On 19x19 ARM2, the reset always brings system to USB download because the
DDR3 turns to unstable.
On the i.MX7D ARM2 board, the WDOG_B signal connects to POR_B or PMIC_PWRON. This gives
a chance to use a stronger reset. So in this patch, we set the IOMUX for WDOG_B pin and
enable WDOG_B signal output in WDOG WCR register.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 1192501c1fcf3b266eb22639a6bc93ac7c03b367)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Implement the auxiliary core booting for Cortex M4 on i.MX7
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit c1c8ba37d87493c16ec1a12bc36d47f909e0e733)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Add HAB files for secure boot and image athentication.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 2447bbcdd4ffcbdbd4ebed1b25e67ea753332d9d)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Generic timer is added to mx7d, so add support for this.
In uboot, only system counter is needed, the timer events are not needed.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 514a79581c6a46df445d69f1fcb2b3bff9584162)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Introduce a new cpu type MXC_CPU_MX7D and relevant functions for mx7d.
Implement the soc.c for various system level functions like:
temperature check, arch init, get mac fuse, boot mode get/apply, etc.
Additional, enable building imx common platform files for mx7d.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 47d65aa6bdd109fd9141b5a5d64ab9deeb9dd2b3)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
Makefile
arch/arm/cpu/armv7/Makefile
arch/arm/imx-common/cpu.c
arch/arm/include/asm/arch-imx/cpu.h
arch/arm/include/asm/imx-common/boot_mode.h
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Since a new CCM with clock root slice is introduced in mx7. Provide
several APIs for configuring root slice in clock_slice.c
Implement clock/PLL relevant functions for modules in mx7d to
enable/disable/set/get clocks or PLLs.
From mx7d, the clocks are initialized in function "void clock_init(void)",
such as UART, USDHC, ECSPI, USB, WDOG, WEIM. These module don't have clock
setting functions in driver and BSP, and assume the clock is setup before
entering into u-boot. Because default root clock is 24Mhz OSC, we have
to setup these default clocks.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 73b511503aef9675e58baadc0639d59c8395bcb4)
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