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* ENGR00325255 pcie:enable pcie support on imx6sx sdRichard Zhu2014-07-31-6/+36
| | | | | | | | | | | | | | Enable pcie support in uboot on imx6sx sd boards - enable_pcie_clock should be call before ssp_en is set, since that ssp_en control the phy_ref clk gate, turn on it after the source of the pcie clks are stable. - add debug info - add rx_eq of gpr12 on imx6sx - there are random link down issue on imx6sx. It's pcie ep reset issue. solution:reset ep, then retry link can fix it. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00322860 iMX6SX: Add function to check M4 status before bootingYe.Li2014-07-17-0/+13
| | | | | | | Add new function "arch_auxiliary_core_check_up" to check whether M4 is already up. Therefore, avoid starting M4 again when it is running. Signed-off-by: Ye.Li <B37916@freescale.com>
* MX6: Correct calculation of PLL_SYSAndre Renaud2014-07-15-1/+1
| | | | | | | | DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do the shift after the multiply to avoid rounding errors Signed-off-by: Andre Renaud <andre@bluewatersys.com> (cherry picked from commit 2eb268f6fd236a5ad9d51e7e47190d7994b3920f)
* mx6: soc: Update the comments of set_ldo_voltage()Fabio Estevam2014-07-15-3/+2
| | | | | | | | | | | | | | | Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces set_ldo_voltage() function that can be used to set the voltages of any of the three LDO regulators controlled by the PMU_REG_CORE register. Prior to this commit there was a single set_vddsoc() which only configured the VDDSOC regulator. Update the comments to align with the new set_ldo_voltage() implementation. Acked-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> (cherry picked from commit 157f45da91b306d71dbf3a51325352dc11bf16d1)
* ENGR00321299 gis: clean csi0 input mux set bit in GPRSandor Yu2014-07-07-0/+6
| | | | | | | | When gis enable in uboot, the CSI0 input mux select setting to vadc module, clean the bit when gis disabled. Signed-off-by: Sandor Yu <R01008@freescale.com> (cherry picked from commit ae66b17b7da3be50dc81ca636b67e8e879f52e26)
* ENGR00321260-1 iMX6: Add support to get CPU serial numberYe.Li2014-07-04-0/+13
| | | | | | | | The android boot needs get_board_serial function to get the CPU uid as the serial number. Implement this function to read the uid from fuse for all iMX6 platforms. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00320350 iMX6SLEVK: Fix build warning of PCIE Phy power downYe.Li2014-06-30-0/+2
| | | | | | | | | | | | Since the iMX6SL does not have PCIE module, should not define the function "imx_set_pcie_phy_power_down" for it. Otherwise, get the build warning below: arch/arm/cpu/armv7/mx6/soc.c:446:13: warning: 'imx_set_pcie_phy_power_down' defined but not used [-Wunused-function] static void imx_set_pcie_phy_power_down(void) Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00319965 pcie: mask the imx6sl outRichard Zhu2014-06-25-2/+7
| | | | | | | imx6sl doesn't have the pcie module, mask the pcie related codes from imx6sl. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00319415 pcie: random link down issue after warm-rstRichard Zhu2014-06-24-0/+18
| | | | | | | | | | | | | | | | | There are about 0.02% percentage on some imx6q/dl/solo hw boards, random pcie link down when warm-reset is used. Make sure to clear the ref_ssp_en bit16 of gpr1 before warm-rst, and set ref_ssp_en after the pcie clks are stable to workaround it. rootcause: * gpr regisers wouldn't be reset by warm-rst, while the ref_ssp_en is required to be reset by pcie. (work-around in u-boot) * ref_ssp_en should be set after pcie clks are stable. (work-around in kernel) Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00315894-77 mx6 soc: Add vadc power up/down functionYe.Li2014-06-17-0/+46
| | | | | | | Add vadc power up/down function. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-76 mx6 clock: Add vadc clock enable functionYe.Li2014-06-17-0/+9
| | | | | | | Add vadc clock enable function. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-71 iMX6SX Update registers and clock for displayYe.Li2014-06-17-0/+199
| | | | | | Add registers and clock functions to enable/set LCDIF clock and LVDS. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-57 iMX6SX: Add M4 boot support at soc levelYe.Li2014-06-17-0/+25
| | | | | | | | | Implement the override function "arch_auxiliary_core_up" to boot Cortex-M4 by executing command "bootaux". The parameter "boot_private_data" points to fields where stores the stack address and PC address for M4 to run. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-54 iMX6SX/SL: Modify SOC to support two ENETYe.Li2014-06-17-4/+64
| | | | | | | | | | | | | | | | | | | | | iMX6SX has different enet system clocks with iMX6SL, and has two ENET controllers. So update clocks and soc APIs accordingly to support this features. 1. Modify the clock API "enable_enet_clock" to enable enet system clock for enet controllers. 2. Enet RGMII TX clock source may come from external or internal PLL. By default, use the external phy CLK_25M output as TX clock source. When using internal PLL as source, the function enable_fec_anatop_clock must be called to enable clock for each enet controller. 3. Modify the MAC address function "imx_get_mac_from_fuse" to get either ENET MAC address. 4. Add configuration "CONFIG_FEC_MXC_25M_REF_CLK" to enable ENET 25Mhz reference clock. 5. Modify imx6slevk BSP to fit the new APIs. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-51 iMX6SX: Add QuadSPI clock enable functionYe.Li2014-06-17-0/+42
| | | | | | | Enable the clock for QuadSPI controllers. Must be called at initialization. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-48 iMX6SX: Add iMX6SX SoC supportYe.Li2014-06-17-2/+47
| | | | | | | | | | | Adding clks, pinmux, memory map, etc for iMX6SoloX. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-35 i.mx6: Fix issue in HAB clock settingYe.Li2014-06-17-9/+9
| | | | | | Should use the address of one register when calling "readl"/"writel". Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-19 iMX6 Disable the L2 before chaning the PL310 latencyYe.Li2014-06-17-0/+3
| | | | | | | | | | | The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. Setting these registers must have PL310 not enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. Thus, disable the PL310 before this setting. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-11 i.mx6:shutdown vddpu and pcie phy to save powerYe.Li2014-06-17-0/+31
| | | | | | | | shutdown vddpu and pcie phy to save power Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315499-21 HDMI: splash screen function enhancementNitin Garg2014-06-13-1/+11
| | | | | | | | | | | | -Change HDMI video mode to VGA. -Add pixel clock fraction part setting in IPU driver, fix video mode timing issue. -Add overflow state clear workaround, fix kernel hang in HDMI driver issue. -Correct IPU clock to 264MHz. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-10 ARM:imx6:sabresd/sabreauto Add android fastboot supportingNitin Garg2014-06-13-0/+94
| | | | | | | | | | | | | | | | | | Support android features: fastboot, booti command and recovery for sabresd SD, sabresd eMMC, sabreauto SD, sabreauto NAND. For all booting media (SD, eMMC, NAND), inherits the partitions layout from v2009.08. Fastboot will detect the booting media to replace hardcoding fastboot device. SATA is not supported. FDT is supported to use the "unused" fields in bootimg header which requires the FDT to be combined into the boot.img. For non-FDT boot.img, the "unused" fields should left to NULL and is compatible to boot. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-6 ARM:imx6: Add USB gadget driver imx_udc to support Android ↵Nitin Garg2014-05-27-0/+50
| | | | | | | | | | | | | | fastboot Android fastboot leans on the USB gadget driver to communicate with host. Porting the imx_udc driver from v2009.08 with two changes: adding resource/memory release APIs and replacing the uncached memory with cache flush&invalidate operations. Pins and Clocks initialization are added to support boards: mx6qdlsabresd, mx6qdlsabreauto, mx6slevk Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-5: Support i.MX6 1.2GHz via LDO bypassNitin Garg2014-05-27-0/+70
| | | | | | | | Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz, enable LDO bypass and setup PMIC voltages. LDO bypass is dependent on the flatten device tree file. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-3: Support i.MX6 HAB authentication of kernel imageNitin Garg2014-05-27-7/+287
| | | | | | | Support HAB authentication of kernel or secondary images via bootm or hab_auth_img u-boot command. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-1: Add i.MX6 CPU temperature sensor supportNitin Garg2014-05-27-1/+136
| | | | | | Support CPU temperature sensors on i.MX6 SoC. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ARM: imx6: fix wrong fec clkMarkus Niebel2014-02-11-1/+1
| | | | | | | | | | imx_get_fecclk() returns enet_ref instead of ipg. Since the clock is used to calculate the prescaler for the MDIO interface wrong values can be calculated. Tested on a custom MX6S board with 100MBit interface Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
* mx6: Enable L2 cache supportFabio Estevam2014-02-11-0/+58
| | | | | | | | | | | Add L2 cache support and enable it by default. Configure the L2 cache in the same way as done by FSL kernel: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Dirk Behme <dirk.behme@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx6: Distinguish mx6dual from mx6quadFabio Estevam2014-02-11-3/+11
| | | | | | | | | | | | Currently when we boot a mx6dual U-boot reports that it is a mx6quad. Report it as MX6D instead: CPU: Freescale i.MX6D rev1.2 at 792 MHz Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* imx6: make sure MMDC_CHx_MASK is clear to avoid warm reset failureAnson Huang2014-02-11-0/+11
| | | | | | | | | Boot ROM may mask MMDC_CHx_MASK in CCM_CCDR(such as i.MX6SL TO1.2), it will cause warm reset fail, need to clear this MMDC_CHx_MASK field to make sure all the i.MX6 series SOCs reset function work. Otherwise, uboot "reset" command will fail, tested on i.MX6SL EVK board with TO1.2. Signed-off-by: Anson Huang <b20788@freescale.com>
* imx6: ensure AHB clock is 132MHz in low freq boot modeAnson Huang2014-02-11-0/+20
| | | | | | | | | | | | For low freq boot mode(ARM boot up with 396MHz), ROM will not set AHB clock to 132MHz, and the reset value of AHB divider is incorrect which will lead to wrong AHB rate, need to correct it. To enable low freq boot mode, need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL SabreSD board and i.MX6SL EVK board. Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Anson Huang <b20788@freescale.com>
* ARM: mx6: Add PCI express clock configurationMarek Vasut2014-01-26-10/+65
| | | | | | | | | | | | | | | | Split the SATA clock enabling function and add PCI express clock enabling function. The SATA clock enabling function starts up the 100MHz SATA reference PLL in ENET_PLL register, but the code can be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull this code into separate function. Moreover, add the PCIe clock enabling code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* mx6: Revert "mx6: soc: Disable VDDPU regulator"Fabio Estevam2014-01-17-41/+0
| | | | | | | | | Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang for people using FSL kernel 3.0.35 and 3.10, so revert it for now. Reported-by: Otavio Salvador <otavio@ossystems.com.br> Reported-by: Pierre Aubert <p.aubert@staubli.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: clock: Pass the frequency as argument of enable_fec_anatop_clock()Fabio Estevam2014-01-15-1/+7
| | | | | | | | | | Provide an argument to enable_fec_anatop_clock() to specify the clock frequency that will be generated. No changes are made to mx6slevk, which uses the default 50MHz fec clock. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx6: make use of lldiv(..)Christian Gmeiner2014-01-13-1/+2
| | | | | | | | | | Commit 762a88ccf8540948fbf8c31b40a29d1e0684a25b introduces a 64-bit division without using the lldiv() function, which pulls in previously unused libgcc stuff. Signed-off-by: Måns Rullgård <mans@mansr.com> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* ARM: mx6: Allow enablement of FEC Anatop based clock for all MX6Otavio Salvador2014-01-03-10/+11
| | | | | | | | | | The enable_fec_anatop_clock method should be available for all MX6 variant as it is not MX6 SoloLite specific. This moves the code out of the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC instead. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
* mx6: soc: Disable VDDPU regulatorFabio Estevam2014-01-02-0/+41
| | | | | | | | | As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: soc: Add the required LDO ramp up delayFabio Estevam2014-01-02-3/+19
| | | | | | | | | | When changing LDO voltages we need to wait for the required amount of time for the voltage to settle. Also, as the timer is still not available when arch_cpu_init() is called, we need to call it later at board_postclk_init() phase. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: soc: Introduce set_ldo_voltage()Fabio Estevam2014-01-02-7/+26
| | | | | | Introduce set_ldo_voltage() so that all three LDO regulators can be configured. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: soc: Set the VDDSOC at 1.175 VFabio Estevam2014-01-02-1/+1
| | | | | | | | | | mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V. Add a 25 mV margin and set it to 1.175V. This also matches the VDDSOC voltages for 792MHz operation that the kernel configures: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltagesFabio Estevam2014-01-02-0/+16
| | | | | | | | | | | | | | Since ROM may modify the LDO ramp up time according to fuse setting, it is safer to reset the ramp up field to its default value of 00: 00: 64 cycles of 24MHz clock; 01: 128 cycles of 24MHz clock; 02: 256 cycles of 24MHz clock; 03: 512 cycles of 24MHz clock; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: soc: Staticize set_vddsoc()Fabio Estevam2014-01-02-1/+1
| | | | | | set_vddsoc() is not used anywhere else, so make it static. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* imx6: fix random hang when download by usbFrank Li2013-12-17-0/+2
| | | | | | | | ROM did not invalidate L1 cache when download by usb Need invalidate L1 cache before enable cache Signed-off-by: Huang yongcai <b20788@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com>
* mx6: clock: Fix the calculation of PLL_ENET frequencyFabio Estevam2013-12-17-1/+1
| | | | | | | | | | | | | | | | According to the mx6 quad reference manual, the DIV_SELECT field of register CCM_ANALOG_PLL_ENETn has the following meaning: "Controls the frequency of the ethernet reference clock. - 00 - 25MHz - 01 - 50MHz - 10 - 100MHz - 11 - 125MHz" Current logic does not handle the 25MHz case correctly, so fix it. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* Merge branch 'iu-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-11-09-14/+42
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile board/compulab/cm_t35/Makefile board/corscience/tricorder/Makefile board/ppcag/bg0900/Makefile drivers/bootcount/Makefile include/configs/omap4_common.h include/configs/pdnb3.h Makefile conflicts are due to additions/removals of object files on the ARM branch vs KBuild introduction on the main branch. Resolution consists in adjusting the list of object files in the main branch version. This also applies to two files which are not listed as conflicting but had to be modified: board/compulab/common/Makefile board/udoo/Makefile include/configs/omap4_common.h conflicts are due to the OMAP4 conversion to ti_armv7_common.h on the ARM side, and CONFIG_SYS_HZ removal on the main side. Resolution is to convert as this icludes removal of CONFIG_SYS_HZ. include/configs/pdnb3.h is due to a removal on ARM side. Trivial resolution is to remove the file. Note: 'git show' will also list two files just because they are new: include/configs/am335x_igep0033.h include/configs/omap3_igep00x0.h
| * mx6: compute PLL PFD frequencies rather than using definesPierre Aubert2013-10-17-14/+42
| | | | | | | | | | Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de>
* | armv7: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-23/+2
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | i2c: mxc: move to new subsystemtrem2013-10-17-1/+1
|/ | | | Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
* mx6: Fix use of improper value in enable_ipu_clockPierre Aubert2013-09-27-1/+1
| | | | | | | | | The value MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET that was used to initialize the CCGR3 register caused an undefined value for CG0. Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
* mx6slevk: Add Ethernet supportFabio Estevam2013-09-20-0/+30
| | | | | | | | mx6slevk has a SMSC8720 connected in RMII mode. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: Fix calculation of emi_slow clock rateAndrew Gabbasov2013-09-10-4/+4
| | | | | | | | | | | | | This is porting of Freescale's patch from version imx_v2009.08_3.0.35_4.0.0, that fixes the obvious mistype of bits offset macro name (ACLK_EMI_PODF_OFFSET was used instead of ACLK_EMI_SLOW_PODF_OFFSET). Using the occasion, change the variable name 'emi_slow_pof' to more consistent 'emi_slow_podf'. Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
generated by cgit v1.1 at 2025-05-08 02:34:28 +0000