| Commit message (Collapse) | Author | Age | Lines |
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For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix
the get_ipg_per_clk function to support it.
Signed-off-by: Ye.Li <B37916@freescale.com>
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THe anatop registers structure is duplicated with CCM structure at
PLL fields.
Since we are suggested not to use the name "anatop" any longer, merge
the anatop registers to the CCM structure "mxc_ccm_reg" and use CCM
to replace anatop.
Signed-off-by: Ye.Li <B37916@freescale.com>
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The QSPI clock rate was set without disabling the clock gate, the
randomly glitch may mess up the clock and there will be no clock output,
when kernel boot up the QSPI access will fail.
To debug this issueon i.MX6SX SDB, changed the u-boot bootscript to 'sf probe; reset'
to keep rebooting, the issue can be reproduced in 20 mins, set clock out
register in CCM and measured TP86, found there is no clock ouput.
To fix this bug, disable clock gate before changing clock rate.
NOTICE: QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, need
to disable both of them.
Signed-off-by: Allen Xu <b45815@freescale.com>
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Enable pcie support in uboot on imx6sx sd boards
- enable_pcie_clock should be call before ssp_en is set,
since that ssp_en control the phy_ref clk gate, turn on
it after the source of the pcie clks are stable.
- add debug info
- add rx_eq of gpr12 on imx6sx
- there are random link down issue on imx6sx. It's
pcie ep reset issue.
solution:reset ep, then retry link can fix it.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do
the shift after the multiply to avoid rounding errors
Signed-off-by: Andre Renaud <andre@bluewatersys.com>
(cherry picked from commit 2eb268f6fd236a5ad9d51e7e47190d7994b3920f)
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Add vadc clock enable function.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Add registers and clock functions to enable/set LCDIF clock and LVDS.
Signed-off-by: Ye.Li <B37916@freescale.com>
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iMX6SX has different enet system clocks with iMX6SL, and has two ENET
controllers. So update clocks and soc APIs accordingly to support this
features.
1. Modify the clock API "enable_enet_clock" to enable enet system clock
for enet controllers.
2. Enet RGMII TX clock source may come from external or internal PLL.
By default, use the external phy CLK_25M output as TX clock source.
When using internal PLL as source, the function enable_fec_anatop_clock
must be called to enable clock for each enet controller.
3. Modify the MAC address function "imx_get_mac_from_fuse" to get either
ENET MAC address.
4. Add configuration "CONFIG_FEC_MXC_25M_REF_CLK" to enable ENET 25Mhz
reference clock.
5. Modify imx6slevk BSP to fit the new APIs.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Enable the clock for QuadSPI controllers. Must be called at
initialization.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Adding clks, pinmux, memory map, etc for iMX6SoloX.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
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Should use the address of one register when calling "readl"/"writel".
Signed-off-by: Ye.Li <B37916@freescale.com>
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Support HAB authentication of kernel or secondary images via bootm
or hab_auth_img u-boot command.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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imx_get_fecclk() returns enet_ref instead of ipg.
Since the clock is used to calculate the prescaler
for the MDIO interface wrong values can be calculated.
Tested on a custom MX6S board with 100MBit interface
Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
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Split the SATA clock enabling function and add PCI express clock
enabling function. The SATA clock enabling function starts up the
100MHz SATA reference PLL in ENET_PLL register, but the code can
be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull
this code into separate function. Moreover, add the PCIe clock
enabling code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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Provide an argument to enable_fec_anatop_clock() to specify the clock frequency
that will be generated.
No changes are made to mx6slevk, which uses the default 50MHz fec clock.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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Commit 762a88ccf8540948fbf8c31b40a29d1e0684a25b introduces
a 64-bit division without using the lldiv() function,
which pulls in previously unused libgcc stuff.
Signed-off-by: Måns Rullgård <mans@mansr.com>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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The enable_fec_anatop_clock method should be available for all MX6
variant as it is not MX6 SoloLite specific. This moves the code out of
the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC
instead.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
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According to the mx6 quad reference manual, the DIV_SELECT field of register
CCM_ANALOG_PLL_ENETn has the following meaning:
"Controls the frequency of the ethernet reference clock.
- 00 - 25MHz
- 01 - 50MHz
- 10 - 100MHz
- 11 - 125MHz"
Current logic does not handle the 25MHz case correctly, so fix it.
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Conflicts:
arch/arm/cpu/arm926ejs/mxs/Makefile
board/compulab/cm_t35/Makefile
board/corscience/tricorder/Makefile
board/ppcag/bg0900/Makefile
drivers/bootcount/Makefile
include/configs/omap4_common.h
include/configs/pdnb3.h
Makefile conflicts are due to additions/removals of
object files on the ARM branch vs KBuild introduction
on the main branch. Resolution consists in adjusting
the list of object files in the main branch version.
This also applies to two files which are not listed
as conflicting but had to be modified:
board/compulab/common/Makefile
board/udoo/Makefile
include/configs/omap4_common.h conflicts are due to
the OMAP4 conversion to ti_armv7_common.h on the ARM
side, and CONFIG_SYS_HZ removal on the main side.
Resolution is to convert as this icludes removal of
CONFIG_SYS_HZ.
include/configs/pdnb3.h is due to a removal on ARM side.
Trivial resolution is to remove the file.
Note: 'git show' will also list two files just because
they are new:
include/configs/am335x_igep0033.h
include/configs/omap3_igep00x0.h
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Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
CC: Stefano Babic <sbabic@denx.de>
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Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
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The value MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET that was used to initialize
the CCGR3 register caused an undefined value for CG0.
Signed-off-by: Pierre Aubert <p.aubert@staubli.com>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
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mx6slevk has a SMSC8720 connected in RMII mode.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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This is porting of Freescale's patch from version imx_v2009.08_3.0.35_4.0.0,
that fixes the obvious mistype of bits offset macro name (ACLK_EMI_PODF_OFFSET
was used instead of ACLK_EMI_SLOW_PODF_OFFSET).
Using the occasion, change the variable name 'emi_slow_pof' to more consistent
'emi_slow_podf'.
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
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Conflicts:
board/freescale/mx6qsabrelite/Makefile
board/freescale/mx6qsabrelite/mx6qsabrelite.c
include/configs/mx6qsabrelite.h
Signed-off-by: Stefano Babic <sbabic@denx.de>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
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Instead of duplicating HDMI setup code for every mx6 board, factor out the common code
Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
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Add an mxc_ocotp driver for i.MX6.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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mx6 solo-lite is another member of the mx6 series.
For more information about mx6 solo-lite, please visit:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6SL&nodeId=018rH3ZrDRB24A
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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If a board does not enable CSPI, there is no need to show the CSPI clock
frequency as part of the 'clock' command.
Reported-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
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Define default SoC input clock frequencies for i.MX5/6 in order to get rid of
duplicated definitions.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Liu <r64343@freescale.com>
Cc: Matt Sealey <matt@genesi-usa.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
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i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using
MXC_I2C_CLK on all imx systems using i2c.
Signed-off-by: Matthias Weisser <weisserm@arcor.de>
Acked-by: Stefano Babic <sbabic@denx.de>
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Add meaningful constants for each clock channels and use them for
enabling and disabling i.MX6 clocks.
Includes an update to enable/disable the IPU1 clock in
drivers/video/ipu_common to remove IMX5x register access
when used on i.MX6 as discussed in V1:
http://patchwork.ozlabs.org/patch/185129/
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
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Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
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Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
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get_ahb_clk() is a common function between mx5 and mx6.
Place it into imx-common directory.
Cc: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Currently, only USB Host 1 is supported.
Cc: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
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Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Acked-by: Stefano Babic <sbabic@denx.de>
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i.MX6Q is freescale quad core processors with ARM cortex_a9 complex.
This patch is to add the initial support for this processor.
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
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