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* ls1021a: adding a secondary core boot address and kick functionsXiubo Li2014-12-11-0/+18
| | | | | | | | | | | | | | | Define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the LS1021A specific manner. Define the board specific smp_kick_all_cpus() functioin to boot a secondary core. Here the BRR contains control bits for enabling boot for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be released for booting or to remain in boot holdoff. All other cores remain in boot holdoff until their corresponding bit is set. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls102xa: Add SD boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+34
| | | | | | | | | | | This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls102xa: clear EPU registers for deep sleepchenhui zhao2014-12-11-0/+142
| | | | | | | | After wakeup from deep sleep, Clear EPU registers as early as possible to prevent from possible issue. It's also safe to clear at normal boot. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls102xa: fixed a bus frequency setting errorTang Yuantian2014-12-11-1/+1
| | | | | | | | The bus frequency in SOC node should be clock frequency of platform. That is not true if it is devided by 2. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls102xa: Add Freescale LS102xA SoC supportWang Huan2014-09-08-0/+681
The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>