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* Merge remote-tracking branch 'u-boot-samsung/master'Albert ARIBAUD2014-07-01-98/+296
|\ | | | | | | | | | | | | | | Conflicts: boards.cfg Conflict was trivial between goni maintainer change and lager_nor removal.
| * Exynos5420: Let macros be used for exynos5420Akshay Saraswat2014-06-23-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Macros defined in exynos5_setup.h specific to SMDK5420 are required for Peach-Pit too. Hence, replacing CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these macros for all the boards based on Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: DMC: Add software read levelingAkshay Saraswat2014-06-13-5/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes Read DQ and DQS are not in phase. Since, this phase shift differs from board to board, we need to calibrate it at DRAM init phase, that's read DQ calibration. This patch adds SW Read DQ calibration routine to compensate this skew. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * DMC: exynos5420: Gate CLKM to when reading PHY_CON13Doug Anderson2014-06-13-5/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when CLKM is running. If we stop CLKM when sampling it the glitches all go away, so we'll do that as per Samsung suggestion. We also check the "is it locked" bits of PHY_CON13 and loop until they show the the value sampled actually represents a locked value. It doesn't appear that the glitching and "is it locked" are related, but it seems wise to wait until the PHY tells us the value is good before we use it. In practice we will not loop more than a couple times (and usually won't loop at all). Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: Remove code for enabling read levelingAkshay Saraswat2014-06-13-71/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch intends to remove all code which enables hardware read leveling. All characterization environments may not cope up with h/w read leveling enabled, so we must disable this. Also, disabling h/w read leveling improves the MIF LVcc value (LVcc value is the value at which DDR will fail to work properly). Improving LVcc means we have enough voltage margin for MIF. When h/w leveling is enabled, we have almost zero volatge margin. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_initAkshay Saraswat2014-06-13-13/+5
| | | | | | | | | | | | | | | | | | | | Passing fewer arguments is better and mem_iv_size is never used. Let's keep only one argument and make it cleaner. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Revert "exynos: Enable PSHOLD in SPL"Minkyu Kang2014-06-13-2/+0
| | | | | | | | This reverts commit eb0dd9986c3883820ff888c3738b013c0a7d918c.
* | cosmetic: Whitespace fixVasili Galka2014-06-11-2/+2
|/ | | | Signed-off-by: Vasili Galka <vvv444@gmail.com>
* Exynos: Make sure ps_hold gets set in the SPLDoug Anderson2014-05-31-1/+11
| | | | | | | | | | | Setting ps_hold ought to be one of the first things we do when we first boot up. If we wait until the main u-boot runs we won't set it in time and the PMIC may power us back off. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: Enable PSHOLD in SPLSimon Glass2014-05-28-0/+2
| | | | | | | | | | | | There is quite a tight deadline in enabling PSHOLD, less than a second. In some cases (e.g. with USB download), U-Boot takes longer than that to load, so the board powers off before U-Boot starts. Add a call in SPL to enable PSHOLD. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: exynos: clock: modify the set_mmc_clk for exynos4Jaehoon Chung2014-05-16-5/+11
| | | | | | | | | | | | Modified the mmc_set_clock for eynos4. The goal of this patch is that fsys-div register should be reset. And retore the div-value, not using the value of lowlevel_init. (For using SDMMC4, this patch is needs) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: exynos: clock: Remove exynos4x12_set_mmc_clk functionBeomho Seo2014-05-16-28/+1
| | | | | | | | | | | | | exynos4x12_set_mmc_clk function have been removed. Because, exynos4x12_clock and exynos4_clock return same div_fsys* value. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: exynos: pinmux: add sdmmc4 gpio configratuionBeomho Seo2014-05-16-6/+29
| | | | | | | | | | | | For use dwmmc controller at exynos4, add SDMMC4 gpio configuration. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Piotr Wilczek <p.wilczek@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* S5P: Exynos: Add GPIO pin numbering and rename definitionsAkshay Saraswat2014-05-13-243/+318
| | | | | | | | | | | | | | | | | | | | | | | This patch includes following changes : * Adds gpio pin numbering support for EXYNOS SOCs. To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them. * Rename GPIO definitions from GPIO_... to S5P_GPIO_... These changes were done to enable cmd_gpio for EXYNOS and cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence getting a error during compilation. * Adds support for name to gpio conversion in s5p_gpio to enable gpio command EXYNOS SoCs. Function has been added to asm/gpio.h to decode the input gpio name to gpio number. Example: SMDK5420 # gpio set gpa00 Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: exynos: Squash bogus warnings in pinmuxMarek Vasut2014-03-13-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Squash these warnings in pinmux.c found with GCC 4.8: /arch/arm/cpu/armv7/exynos/pinmux.c: In function 'exynos_pinmux_config': /arch/arm/cpu/armv7/exynos/pinmux.c:687:28: warning: 'count' may be used uninitialized in this function [-Wmaybe-uninitialized] for (i = start; i < start + count; i++) { ^ /arch/arm/cpu/armv7/exynos/pinmux.c:663:16: note: 'count' was declared here int i, start, count; ^ /arch/arm/cpu/armv7/exynos/pinmux.c:687:28: warning: 'start' may be used uninitialized in this function [-Wmaybe-uninitialized] for (i = start; i < start + count; i++) { ^ /arch/arm/cpu/armv7/exynos/pinmux.c:663:9: note: 'start' was declared here int i, start, count; ^ /arch/arm/cpu/armv7/exynos/pinmux.c:689:19: warning: 'bank' may be used uninitialized in this function [-Wmaybe-uninitialized] s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); ^ /arch/arm/cpu/armv7/exynos/pinmux.c:662:24: note: 'bank' was declared here struct s5p_gpio_bank *bank; ^ /arch/arm/cpu/armv7/exynos/pinmux.c: In function 'exynos_pinmux_config': /arch/arm/cpu/armv7/exynos/pinmux.c:687:28: warning: 'count' may be used uninitialized in this function [-Wmaybe-uninitialized] for (i = start; i < start + count; i++) { ^ /arch/arm/cpu/armv7/exynos/pinmux.c:663:16: note: 'count' was declared here int i, start, count; ^ /arch/arm/cpu/armv7/exynos/pinmux.c:687:28: warning: 'start' may be used uninitialized in this function [-Wmaybe-uninitialized] for (i = start; i < start + count; i++) { ^ /arch/arm/cpu/armv7/exynos/pinmux.c:663:9: note: 'start' was declared here int i, start, count; ^ /arch/arm/cpu/armv7/exynos/pinmux.c:689:19: warning: 'bank' may be used uninitialized in this function [-Wmaybe-uninitialized] s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); ^ /arch/arm/cpu/armv7/exynos/pinmux.c:662:24: note: 'bank' was declared here struct s5p_gpio_bank *bank; ^ Note that the warning is bogus, the function can never be called with invalid 'peripheral' argument. GCC just cannot analyze this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@ti.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos4:pinmux:fdt: decode peripheral idPiotr Wilczek2014-03-12-0/+17
| | | | | | | | This patch adds api to decode peripheral id based on interrupt number. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: clock: use the clear and set bits macros.Inha Song2014-02-10-65/+20
| | | | | | | | | Use setbits/clrbits macro instead of readl/writel function. (Suggested by Wolfgang) Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: clock: fixed that cfg is set to wrong value.Inha Song2014-02-10-0/+3
| | | | | | | | | This patch fixed that cfg value is set to wrong value. Because it didn't read the related register. Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: pinmux: remove unnecessary routineMinkyu Kang2014-02-05-6/+1
| | | | | | | | | | Because of the list of peripherals is not sequential, such a routine does not check for valid correctly. Error check will be done when call the exynos_pinmux_config function. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
* exynos: pinmux: remove unnecessary defineMinkyu Kang2014-02-05-1/+1
| | | | | | The value of PERIPH_ID_COUNT was wrong, and unnecessary. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: put .hash, .got.plt and .machine_param back in binariesAlbert ARIBAUD2014-01-14-0/+7
| | | | | | | | | | | Some targets will build fine but not boot if sections .hash and .got.plt are not present in the binary. Add them back. Also, Exynos machines require .machine_param section in SPL. Add it. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Tested-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
* Exynos5420: Add support for 5420 in pinmux and gpioRajeshwari Birje2013-12-30-2/+258
| | | | | | | | | | Adds code in pinmux and gpio framework to support Exynos5420. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5420: Add DDR3 initialization for 5420Rajeshwari Birje2013-12-30-56/+469
| | | | | | | | | This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5420: Add clock initialization for 5420Rajeshwari Birje2013-12-30-202/+1184
| | | | | | | | | | This patch adds code for clock initialization and clock settings of various IP's and controllers, required for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: exynos: adds ifdef for spi bootMinkyu Kang2013-12-06-0/+4
| | | | | | | | | | | | | | | | This patch fix following errors and warnings spl_boot.c: In function 'exynos_spi_copy': spl_boot.c:111:49: error: 'CONFIG_ENV_SPI_BASE' undeclared (first use in this function) spl_boot.c:111:49: note: each undeclared identifier is reported only once for each function it appears in spl_boot.c:142:2: error: 'SPI_FLASH_UBOOT_POS' undeclared (first use in this function) spl_boot.c: In function 'copy_uboot_to_ram': spl_boot.c:189:28: warning: unused variable 'param' [-Wunused-variable] spl_boot.c: At top level: spl_boot.c:107:13: warning: 'exynos_spi_copy' defined but not used [-Wunused-function] Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* exynos: spl: Add a custom spi copy functionRajeshwari Shinde2013-12-03-4/+120
| | | | | | | | | | | | | | This patch implements a custom spi_copy funtion to copy u-boot from SF to RAM. This is faster then iROM spi_copy funtion as this runs spi at 50Mhz and also in WORD mode of operation. Changed a printf in pinmux.c to debug just to avoid the compilation error in SPL. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: exynos: fix set_mmc_clk for exynos4x12Jaehoon Chung2013-12-03-1/+2
| | | | | | | | Fix the set_mmc_clk() for exnos4x12. If board is exynos4x12, mmc clock should be set to wrong value. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* armv7: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-28/+6
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* arm: exynos: Add methods to control power to USB 3.0 PHYVivek Gautam2013-10-20-0/+22
| | | | | | | | | | | | Adding methods to turn on/off power to USB3.0 type PHY as and when required by the controller. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
* ARM: Added I2S0 clocks for audioDani Krishna Mohan2013-09-24-21/+63
| | | | | | | | This patch makes the necessary changes for making use of I2S0 channel instead of I2S1 channel on smdk board. This changes are done to maintain the uniformity to use I2S0 channel. Signed-off-by: Dani Krishna Mohan <krishna.md@samsung.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-235/+14
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* arm:exynos:fix: Fix clock calculation for Exynos4210 based targets.Łukasz Majewski2013-07-16-5/+4
| | | | | | | | | | | Provide proper setting for the APLL fout frequency calculation for Exynos4 based targets (especially Exynos4210 - Trats board). Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* arm: exynos: fix clock calculationMinkyu Kang2013-07-09-5/+38
| | | | | | | | There are differnce with clock calcuation by cpu variations. This patch will fix it according to user manual. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
* EXYNOS: Move files from board/samsung to arch/armRajeshwari Shinde2013-07-05-4/+3074
| | | | | | | | | | | | | | | | | | | | This patch performs the following: 1) Convert the assembly code for memory and clock initialization to C code. 2) Move the memory and clock init codes from board/samsung to arch/arm 3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted the common lowlevel_init from assembly to C-code 4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5. 5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already done in _main. 6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250. TEST: Tested SD-MMC boot on SMDK5250 and Origen. Tested USB and SPI boot on SMDK5250 Compile tested for SMDKV310. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS4210: Configure GPIO for uartRajeshwari Shinde2013-07-05-0/+40
| | | | | | | | | This patch configures the gpio values for UART on Origen and SMDKV310 using pinmux Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS: Add API for power reset and exit wakeupRajeshwari Shinde2013-07-05-0/+50
| | | | | | | | This patch adds APIs to get power reset status and exit the wakeup condition for both exynos5 and exynos4 Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: DWMMC: Initialise the local variable to avoid unwanted results.Amar2013-06-13-2/+2
| | | | | | | | | | | | This patch initialises the local variable 'shift' to zero. The uninitialised local variable 'shift' had garbage value and was resulting in unwnated results in the functions exynos5_get_mmc_clk() and exynos4_get_mmc_clk(). Signed-off-by: Amar <amarendra.xt@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: update tzpc to make it common for exynos4 and exynos5Inderpal Singh2013-06-04-7/+16
| | | | | | | | | | This requires that cpu_is_exynos4/5 should be made available before tzpc_init. Hence this patch also makes necessary changes to have cpu_info in spl and invokes arch_cpu_init before tzpc_init in low_level_init.S for smdk5250. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: move tzpc_init to armv7/exynosInderpal Singh2013-06-04-1/+49
| | | | | | | | | | | tzpc_init is common for all exynos5 boards, hence move it to armv7/exynos so that all other boards can use it. Also update the smdk5250 Makefile and config file. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5: clock: Update the equation to calculate PLL output frequencyAkshay Saraswat2013-05-21-4/+2
| | | | | | | | | | | | | | According to the latest exynos5 user manual, the equation for calculating PLL output was changed to FOUT= MDIV x FIN/(PDIV x 2^SDIV) earlier it was FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1)) So updating the clock code accordingly. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: pwm: Remove dead code of function exynos5_get_pwm_clkAkshay Saraswat2013-04-01-21/+0
| | | | | | | | | As we shall now be using clock_get_periph_rate function. We find no reason for keeping code in function exynos5_get_pwm_clk. Hence, removing it. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: pwm: Use generic api to get pwm clk freqPadmavathi Venna2013-04-01-1/+1
| | | | | | | | | | | | | Use generic api to get the pwm clock frequency Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: clock: Add generic api to get the clk freqPadmavathi Venna2013-04-01-0/+144
| | | | | | | | | | | | | | | Add generic api to get the frequency of the required peripherial. This API gets the source clock frequency and returns the required frequency by dividing with first and second dividers based on the requirement. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: Add L2 Cache Support.Rajeshwari Shinde2013-03-27-0/+36
| | | | | | | | | This patch set adds L2 Cache Support to EXYNOS. Signed-off-by: Arun Mankuzhi <arun.m@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5: TMU: Add hardware trippingAkshay Saraswat2013-03-12-0/+12
| | | | | | | | | This adds hardware tripping at 110 degrees celsius which must enable forced system shutdown in case TMU fails to power off. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: Add function to enable XXTI clock sourceRajeshwari Shinde2013-03-08-0/+17
| | | | | | | | This patch adds funtion to enable XXTI clock source required by MAX98095 codec. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: Add function to setup set ps holdRajeshwari Shinde2013-02-20-0/+16
| | | | | | | | | | This patch adds a function to set ps_hold data driving value high. This enables the machine to stay powered on even after the initial power-on condition goes away(e.g. power button). Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: clock: add CLK_DIV_FSYS3 at set_mmc_clkJaehoon Chung2013-01-11-0/+5
| | | | | | | | Mobile storage is used the CLK_DIV_FSYS3 value. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: clock: support get_mmc_clk for exynosJaehoon Chung2013-01-11-0/+102
| | | | | | | | | To get exactly clock value for mmc, support the get_mmc_clk() like set_mmc_clk(). Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: Change parent clock of FIMD to MPLLAjay Kumar2013-01-10-1/+1
| | | | | | | | | | | With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit v1.1 at 2024-10-31 19:23:57 +0000