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* ARM: AM43xx: EPOS_EVM: Add support for LPDDR2Lokesh Vutla2013-12-18-1/+21
| | | | | | | | | | | | | | | AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM33xx+: Update ioregs to pass different valuesLokesh Vutla2013-12-18-3/+2
| | | | | | | | | | | Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: Tom Rini <trini@ti.com>
* Add TI816X supportTENART Antoine2013-08-15-0/+6
| | | | | | Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Fix warnings about vtp things in emif4.c, adapt AM43XX] Signed-off-by: Tom Rini <trini@ti.com>
* ARM: AM33xx: Cleanup clocks layerLokesh Vutla2013-08-15-1/+0
| | | | | | | | | | | Cleaning up the clocks layer. This helps in addition of new Soc with minimal changes. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* ARM: AM33xx: Cleanup dplls dataLokesh Vutla2013-08-15-0/+4
| | | | | | | | | | | | | Locking sequence for all the dplls is same. In the current code same sequence is done repeatedly for each dpll. Instead have a generic function for locking dplls and pass dpll data to that function. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* am335x_evm: Add support to boot from NOR.Steve Kipisz2013-07-30-1/+5
| | | | | | | | | | | | | | | | | | NOR requires that s_init be within the first 4KiB of the image so that we can perform the rest of the required pinmuxing to talk with the rest of NOR that we are found on. When NOR_BOOT is set we save our environment in NOR at 512KiB and a redundant copy at 768KiB. We avoid using SPL for this case and u-boot.bin is written directly to the start of NOR. We enclose the DMM-related parts of arch/arm/cpu/armv7/am33xx/emif4.c with TI81xx checks as at this time U-Boot does not discard unused sections in the main build and this code relies on functions specific to (and only provided in) ti81xx-related code. Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-9/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: add dmm support to emif4 libraryMatt Porter2013-03-24-0/+17
| | | | | | | Adds a config_dmm() routine to support TI814X DMM configuration. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* am33xx: refactor emif4/ddr to support multiple EMIF instancesMatt Porter2013-03-24-18/+22
| | | | | | | | | | The AM33xx emif4/ddr support closely matches what is need to support TI814x except that TI814x has two EMIF instances. Refactor all the emif4 helper calls and the config_ddr() init function to use an additional instance number argument. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* am33xx: support board specific ddr settingsPeter Korsgaard2012-10-25-103/+11
| | | | | | | | | Move the hardcoded ddr2/ddr3 settings for the ti boards to board code, so other boards can use different types/timings. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> [trini: Make apply with rtc32k_enable() in the file] Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and supportTom Rini2012-09-01-0/+41
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework config_ddr to make DDR3 support easier.Tom Rini2012-09-01-14/+23
| | | | | | | | In order to support DDR3 as well as DDR2, we need to perform the same init sequence, but with different values. So change config_ddr() to toggle setting pointers/etc for what DDR2 wants, and then calling. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Move some variables in emif4.c, mark them static.Tom Rini2012-09-01-4/+3
| | | | | | We need vtpreg and ddrctrl but no longer need a second ddrregs. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Correct and clean up ddr_regs structTom Rini2012-09-01-9/+1
| | | | | | | | | | | | | | The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry. Correct this by documenting a missing register that will be used at some point in the future (when write leveling is supported). Further, the cmdNcs{force,delay} fields are undocumented and we have been setting them to zero, remove. Next, setting of the 'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the ddr_data entries, so program it there. Finally, comment on how we are configuring the DATA1 registers that correspond to the DATA0 (dt0) registers defined in the struct. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Do not touch 'ratio1' fieldsTom Rini2012-09-01-6/+0
| | | | | | | | | The various ratio1 fields are not documented in any of the documentation I can find. Removing these and testing has yielded success, so remove the code that sets them and move their locations into the reserved fields. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework config_io_ctrl slightlyTom Rini2012-09-01-9/+1
| | | | | | | | | This function sets a number of related registers to the same value (the registers in question all have the same field descriptions and are related in operation). Rather than defining a struct and setting the value repeatedly, just pass in the value. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Use emif_regs struct for storing initialization valuesTom Rini2012-09-01-30/+13
| | | | | | | Rather than defining our own structs to note what to use when programming the EMIF and related re-use the emif_regs struct. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Turn a number of 'int' functions to 'void'Tom Rini2012-09-01-13/+3
| | | | | | | | A number of memory initalization functions were int and always returned 0. Further it's not feasible to be doing error checking here, so simply turn them into void functions. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Document what we're doing with ddrctrl->ddrckectrlTom Rini2012-09-01-4/+2
| | | | | | | | | - Remove the call to set ddrctrl->ddrioctrl as it's all zeros. - Comment what we're really setting in ddrctrl->ddrckectrl which is that we're operating in the normal mode where EMIF/PHY clock is controlled by the PHY. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Clean up unused DDR defines, prefix more with 'DDR2'Tom Rini2012-09-01-23/+23
| | | | | | | - Remove a handful of unused defines. - Prefix more values with 'DDR2' as DDR3 will require different values. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Move the call to ddr_pll_config, make it take the frequencyTom Rini2012-09-01-0/+2
| | | | | | | | Depending on if we have DDR2 or DDR3 on the board we will need to call ddr_pll_config with a different value. This call can be delayed slightly to the point where we know which type of memory we have. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Pass to config_ddr the type of memory that is connectedTom Rini2012-09-01-17/+21
| | | | | | | | | We need to pass in the type of memory that is connected to the board. The only reliable way to do this is to know what type of board we are running on (which later will be knowable in s_init()). For now, pass in the value of DDR2. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Make config_cmd_ctrl / config_ddr_data take const structsTom Rini2012-09-01-57/+44
| | | | | | | | | Rework the EMIF4/DDR code slightly to setup the structs that config_cmd_ctrl and config_ddr_data take to be setup at compile time and mark them as const. This lets us simplify the calling path slightly as well as making it easier to deal with DDR3. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework DDR2 EMIF initalization slightlyTom Rini2012-09-01-15/+2
| | | | | | | With the previous bugfix we now don't need to set two different REF_CTRL values and instead set the final value. Signed-off-by: Tom Rini <trini@ti.com>
* ARM:AM33XX: Add SPL support for AM335X EVMChandan Nath2012-01-16-1/+1
| | | | | | | | | | | This patch is added to support SPL feature on AM335X platform. In this patch, MMC1 is configured as boot device for SPL and support for other devices will be added in the next patch series. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* ARM:AM33XX: Add emif/ddr supportChandan Nath2011-10-27-0/+201
This patch adds AM33xx emif/ddr support along with board specific defines. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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