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* ARM: AM43xx: Write sdram_config to secure_emif_sdram_configDave Gerlach2014-03-04-0/+1
| | | | | | | | | The register secure_emif_sdram_config in control module is copied to the EMIF sdram_config register when it is coming out of DeepSleep0 in order to ensure that the EMIF comes up for the correct type of DDR. Without this, resume can hang from within the kernel. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* ARM: AM43xx: EMIF: configure self-refresh entry delayDave Gerlach2014-03-04-2/+2
| | | | | | | | | | Per a suggestion from the hardware team, program the emif_pwr_mgmt_ctrl and emif_pwr_mgmt_ctrl_shdw registers within the EMIF to hold the desired delay in cycles that the EMIF waits without an access to enter self-refresh, in this case 8192 cycles. With this, code desiring to enter self refresh only has to toggle one bit to enable it. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* ARM: AM43xx: GP_EVM: Add support for DDR3Lokesh Vutla2013-12-18-2/+4
| | | | | | | | | | | | | | | | GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: EPOS_EVM: Add support for LPDDR2Lokesh Vutla2013-12-18-0/+117
| | | | | | | | | | | | | | | AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM33xx+: Update ioregs to pass different valuesLokesh Vutla2013-12-18-6/+21
| | | | | | | | | | | Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Stop modifying certain EMIF4D registersTom Rini2013-12-04-7/+0
| | | | | | | | | | | | | | | Based on the definitive guide to EMIF configuration[1] certain registers that we have been modifying (and are documented registers) should be left in their reset values rather than modified. This has been tested on AM335x GP EVM and Beaglebone White. [1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Javier Martinez Canillas <javier@dowhile0.org> Cc: Heiko Schocher <hs@denx.de> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Matt Porter <matt.porter@linaro.org>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-11/+2
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: refactor emif4/ddr to support multiple EMIF instancesMatt Porter2013-03-24-44/+63
| | | | | | | | | | The AM33xx emif4/ddr support closely matches what is need to support TI814x except that TI814x has two EMIF instances. Refactor all the emif4 helper calls and the config_ddr() init function to use an additional instance number argument. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* am33xx:ddr:Fix config_sdram to work for all DDRSteve Kipisz2013-03-22-1/+4
| | | | | | | | | | | | | The original write to sdram_config is correct for DDR3 but incorrect for DDR2 so SPL was hanging. For DDR2, the write to sdram_config should be after the writes to ref_ctrl. This was working for DDR3 because there was a write of 0x2800 to ref_ctrl before a write to sdram_config. Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3), Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3) Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
* am33xx: Update DDR3 EMIF configuration sequenceTom Rini2013-03-08-3/+9
| | | | | | | | | | Based on http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips we need to re-work our sequence in config_sdram slightly to match what the TRM describes as the correct sequence. In our current (incorrect) sequence some edge cases may fail to initalize correctly. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx evm: Update secure_emif_sdram_config during ddr initSatyanarayana, Sandhya2012-09-01-1/+4
| | | | | | | | | | | | | | | This patch updates secure_emif_sdram_config with the same value written to sdram_config during ddr3 initialization. During suspend/resume, this value is copied into sdram_config. With this, a write to sdram_config at the end of resume sequence which triggers an init sequence can be avoided. Without this register write in place, the DDR_RESET line goes low for a few cycles during resume which is a violation of the JEDEC spec. Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
* am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and supportTom Rini2012-09-01-0/+2
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Correct and clean up ddr_regs structTom Rini2012-09-01-6/+1
| | | | | | | | | | | | | | The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry. Correct this by documenting a missing register that will be used at some point in the future (when write leveling is supported). Further, the cmdNcs{force,delay} fields are undocumented and we have been setting them to zero, remove. Next, setting of the 'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the ddr_data entries, so program it there. Finally, comment on how we are configuring the DATA1 registers that correspond to the DATA0 (dt0) registers defined in the struct. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Do not touch 'ratio1' fieldsTom Rini2012-09-01-11/+0
| | | | | | | | | The various ratio1 fields are not documented in any of the documentation I can find. Removing these and testing has yielded success, so remove the code that sets them and move their locations into the reserved fields. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework config_io_ctrl slightlyTom Rini2012-09-01-6/+6
| | | | | | | | | This function sets a number of related registers to the same value (the registers in question all have the same field descriptions and are related in operation). Rather than defining a struct and setting the value repeatedly, just pass in the value. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Use emif_regs struct for storing initialization valuesTom Rini2012-09-01-14/+14
| | | | | | | Rather than defining our own structs to note what to use when programming the EMIF and related re-use the emif_regs struct. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Turn a number of 'int' functions to 'void'Tom Rini2012-09-01-23/+6
| | | | | | | | A number of memory initalization functions were int and always returned 0. Further it's not feasible to be doing error checking here, so simply turn them into void functions. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Make config_cmd_ctrl / config_ddr_data take const structsTom Rini2012-09-01-2/+2
| | | | | | | | | Rework the EMIF4/DDR code slightly to setup the structs that config_cmd_ctrl and config_ddr_data take to be setup at compile time and mark them as const. This lets us simplify the calling path slightly as well as making it easier to deal with DDR3. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Bugfix to config_sdram()Tom Rini2012-09-01-2/+1
| | | | | | | When we change SDRAM_CONFIG this triggers a refresh based on all of the parameters that we have programmed so we must do this last. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Convert to using <asm/emif.h> to describe the EMIFTom Rini2012-09-01-14/+15
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* ARM:AM33XX: Add emif/ddr supportChandan Nath2011-10-27-0/+147
This patch adds AM33xx emif/ddr support along with board specific defines. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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