summaryrefslogtreecommitdiff
path: root/arch/arm/cpu/armv7/am33xx/clock.c
Commit message (Collapse)AuthorAgeLines
* arm:am33xx: Add a scale_vcores() hookTom Rini2014-06-06-0/+11
| | | | | | | Similar to OMAP4/5 we need to scale the voltage up prior to changing the clock frequencies up higher. Add a similar hook to start with. Signed-off-by: Tom Rini <trini@ti.com>
* ARM: AM43xx: clocks: Update DPLL detailsLokesh Vutla2013-12-18-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM33xx: Cleanup clocks layerLokesh Vutla2013-08-15-1/+61
| | | | | | | | | | | Cleaning up the clocks layer. This helps in addition of new Soc with minimal changes. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* ARM: AM33xx: Cleanup dplls dataLokesh Vutla2013-08-15-0/+111
| | | | | | | | | | | | | Locking sequence for all the dplls is same. In the current code same sequence is done repeatedly for each dpll. Instead have a generic function for locking dplls and pass dpll data to that function. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* am33xx: refactor am33xx clocks and add ti814x supportMatt Porter2013-03-24-374/+0
| | | | | | | Split clock.c for am335x and ti814x and add ti814x specific clock support. Signed-off-by: Matt Porter <mporter@ti.com>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-08-0/+10
|\ | | | | | | | | This required manual merging drivers/mtd/nand/Makefile and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS
| * am33xx: add ELM supportMansoor Ahamed2012-12-10-0/+5
| | | | | | | | | | | | | | | | | | AM33XX has Error Location Module (ELM) that can be used in conjuction with GPMC controller to implement BCH codes fully in hardware. This code is mostly taken from arago tree. Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com> Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * am33xx: NAND supportIlya Yanok2012-12-10-0/+5
| | | | | | | | | | | | | | | | TI AM33XX has the same GPMC controller as OMAP3 so we could just use the existing omap_gpmc driver. This patch adds adds required definitions/intialization. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* | am33xx: init OTG hardware and new musb gadget driverIlya Yanok2012-11-20-0/+8
|/ | | | | | | | AM33xx has support for dual port MUSB OTG controller. This patch adds initialization for the controller using new MUSB gadget driver and ether gadget. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* am33xx: Enable UART{1,2,3,4,5} clocksAndrew Bradford2012-10-25-0/+35
| | | | | | | | If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232 cape or the am335x_evm daughterboard, enable the required clocks for the UART in use. Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
* am335x: Enable RTC 32K OSC clockVaibhav Hiremath2012-10-25-0/+6
| | | | | | | | | | | | | | | | | In order to support low power state, you must source kernel system timers to persistent clock, available across suspend/resume. In case of AM335x device, the only source we have is, RTC32K, available in wakeup/always-on domain. Having said that, during validation it has been observed that, RTC clock need couple of seconds delay to stabilize the RTC OSC clock; and such a huge delay is not acceptable in kernel especially during early init and also it will impact quick/fast boot use-cases. So, RTC32k OSC enable dependency has been shifted to SPL/first-bootloader. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Add support, update omap3 McSPI driverTom Rini2012-09-01-0/+5
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Move the call to ddr_pll_config, make it take the frequencyTom Rini2012-09-01-3/+2
| | | | | | | | Depending on if we have DDR2 or DDR3 on the board we will need to call ddr_pll_config with a different value. This call can be delayed slightly to the point where we know which type of memory we have. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Remove extra check in enable_ddr_clocksTom Rini2012-09-01-5/+0
| | | | | | | We do not need to check for EMIF_GCLK and L3_GCLK being active. This was a hold-over from bringup and no longer required. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Enable gpio0 clockTom Rini2012-09-01-0/+4
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: CPSW init and definitionsChandan Nath2012-09-01-1/+7
| | | | | | | | | This patch adds platform-specific initialization for CPSW switch on TI AM33XX SoCs. Signed-off-by: Chandan Nath <chandan.nath@ti.com> [Ilya: split init out of original patch] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* omap: am335x_evm: enable i2c1 channelSteve Sakoman2012-09-01-0/+5
| | | | | | | This patch sets up pinmux, enables fclk, and defines CONFIG_I2C_MULTI_BUS Signed-off-by: Steve Sakoman <steve@sakoman.com>
* omap: am33xx: enable gpio supportSteve Sakoman2012-09-01-0/+15
| | | | | | | | | | | This patch uses the code in omap-common to support gpio modules 1-3 on am33xx based boards. It adds base address and register definitions, enables clocks to the modules, and enables building the common gpio code for CONFIG_AM33XX as well as CONFIG_OMAP Signed-off-by: Steve Sakoman <steve@sakoman.com>
* ARM: AM33XX: Add i2c supportPatil, Rachna2012-01-23-0/+5
| | | | | | | Add i2c driver board hookup for AM335X EVM Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Patil, Rachna <rachna@ti.com>
* ARM:AM33XX: Add mmc/sd supportChandan Nath2012-01-16-0/+5
| | | | | | | | | This patch add supports for mmc/sd driver on AM335X platform. PLL and pinmux configurations for mmc/sd are configured in this patch. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* ARM:AM33XX: Fix ddr and timer register offsetChandan Nath2012-01-16-0/+3
| | | | | | | | This patch is added to update incorrect ddr and timer register offset. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* ARM:AM33XX: Add clock definitionsChandan Nath2011-10-27-0/+273
This patch adds basic clock definition of am33xx SoC. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
generated by cgit v1.1 at 2024-11-18 19:11:41 +0000