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* Consolidate bootcount code into drivers/bootcountStefan Roese2012-09-01-26/+0
| | | | | | | | | | | | | | | | | | | This patch moves all bootcount implementations into a common directory: drivers/bootcount. The generic bootcount driver is now usable not only by powerpc platforms, but others as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Christian Riesch <christian.riesch@omicron.at> Cc: Manfred Rudigier <manfred.rudigier@omicron.at> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de> Tested-by: Valentin Longchamp <valentin.longchamp@keymile.com> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* ARM: mx28: Remove CONFIG_ARCH_CPU_INITFabio Estevam2012-07-07-2/+0
| | | | | | | | | No need to define CONFIG_ARCH_CPU_INIT. All mx28 based boards should use arch_cpu_init(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* SPL: ARM: spear: Add SPL support for SPEAr600 platformStefan Roese2012-07-07-7/+1480
| | | | | | | | | | | | This patch adds SPL support for SPEAr600. Currently only SNOR (Serial NOR) flash support is included. Other boot devices (NAND, MMC, USB ...) may be added with later patches. Tested on the STM SPEAr600 evaluation and x600 SPEAr600 boards. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Amit Virdi <amit.virdi@st.com> Cc: Vipin Kumar <vipin.kumar@st.com>
* SPEAr: explicitly select clk src for UARTShiraz Hashim2012-07-07-1/+6
| | | | | | | | | | UART in u-boot intends to run on 48MHz clock supplied by USB PLL. Explicitly select the intended clock source. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* SPEAr: Add basic arch related support for SPEAr SoCsVipin KUMAR2012-07-07-1/+84
| | | | | | | | | | | Earlier, architecture specific init code was mixed with board initialization code in board/spear/... This patch updates architecture support for SPEAr in latest u-boot and prints the SoC information. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* kirkwood: add save functionality kirkwood_mpp_conf functionValentin Longchamp2012-07-07-1/+9
| | | | | | | | | | | | | | If a second non NULL argument is given to the kirkwood_mpp_conf function, it will be used to store the current configuration of the MPP registers. mpp_save must be a preallocated table of the same size as mpp_list and it must be zero terminated as well. A later call to kirkwood_mpp_conf function with this saved list as first (mpp_conf) argment will set the configuration back. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
* i.MX28: Add function to adjust memory parametersMarek Vasut2012-07-07-0/+8
| | | | | | | | | | | | | | This function can be overridden at run-time and allows implementors of new boards based on the i.MX28 chip to fine-tune the memory params. It is possible to write into the dram_vals array because when the SPL runs, it is located SRAM. Therefore the location is writable. There is no possibility of these data to be read-only. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
* DaVinci: fix ddr2 vtp i/o calibrationTroy Kisky2012-07-07-4/+3
| | | | | | | | | | | | | | | | | | | | | Previously, only the low 5 bits (NCH) were being transfered from DDRVTPR to DDRVTPIOCR, the bits 5-9 where zeroed. VTP_RECAL should be bit 15, not 18. The only mainline board affected by this change is davinci_sonata. The other Davinci boards define CONFIG_SKIP_LOWLEVEL_INIT. However, if the program that loads u-boot on these boards copied the code from u-boot, they will need fixed as well. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Please get tested by acks before applying, where tested by means an overnight memory test. Thanks Troy
* i.MX28: Avoid redefining serial_put[cs]()Marek Vasut2012-05-15-0/+2
| | | | | | | | | | | | Do not define serial_putc() and serial_puts() calls if CONFIG_SPL_SERIAL_SUPPORT is set. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX28: Add battery boot components to SPLMarek Vasut2012-05-15-8/+92
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Reorder battery status functions in SPLMarek Vasut2012-05-15-64/+56
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Add LRADC init to i.MX28 SPLMarek Vasut2012-05-15-1/+100
| | | | | | | | | | This code is part of battery boot support for i.MX28. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Shut down the LCD controller before resetMarek Vasut2012-05-15-1/+8
| | | | | | | | | | | | If the LCD controller is on before the CPU goes into reset, the traffic on LCDIF data pins interferes with the BootROM's boot mode sampling. So shut the controller down. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Implement boot pads sampling and reportingMarek Vasut2012-05-15-0/+52
| | | | | | | | | | | This patch implements code that samples i.MX28 boot pads and reports boot mode accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Improve passing of data from SPL to U-BootMarek Vasut2012-05-15-18/+16
| | | | | | | | | | | | Pass memory size from SPL via structure located in SRAM instead of SCRATCH registers. This allows passing more data about boot from SPL to U-Boot, like the boot mode pads configuration. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Add delay after CPU bypass is clearedMarek Vasut2012-05-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This solves issues when larger amount of DRAM is used, like 256MB. Behave the same in case of CPU bypass as we do in case of EMI bypass, but wait 15 ms. We need to wait until the clock domain stabilizes. This issue seemed to have been caused by not waiting after frobbing with the CPU bypass, it was unrelated to memory, but had a direct impact, causing trouble. This was yet another X-File of the imx-bootlets, sigh. The conclusion is, trying a semi-random delay (there is delay after the EMI bypass change), the issue is fixed. Another possible explanation is that we do not do the "simple memory test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of the memory, while also outputing something on the serial port). This might have caused the similar delay in the imx-bootlets and therefore they didn't need to add this explicitly. For now, this seems good fix enough, but to me, whole that memory init code in imx-bootlets is completely flunked and it'd need deeper investigation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
* imx: Add u-boot.imx as target for ARM9 i.MX SOCsTimo Ketola2012-05-15-0/+6
| | | | | Signed-off-by: Timo Ketola <timo@exertus.fi> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX25: esdhc: Add mxc_get_clock infrastructureTimo Ketola2012-05-15-0/+27
| | | | | | | | | Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's implement get_clocks function. This is how it seems to be implemented elsewhere. Signed-off-by: Timo Ketola <timo@exertus.fi> Acked-by: Stefano Babic <sbabic@denx.de>
* Revert "i.MX28: Enable additional DRAM address bits"Marek Vasut2012-05-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 69d26d09de1cb93e0a09ca71d9f0d41a66f0756a. Apparently, this commit got mainline only because of out-of-tree port and causes breakage on board that is mainline. Revert. Reason: * The OOT board has 512MB of DRAM, enabling this additional address line enabled it to work fine with 512MB of RAM. * Every mainline port has max. 256MB of DRAM, therefore this revert has no impact on any mainline port * Though this caused a problem with new M28 board with 256MB of DRAM where the chips are wired differently. The patch-to-be-reverted caused the DRAM to behave like this: [128MB chunk #1][128MB chunk #1 again][128MB chunk #2][128MB chunk #2 again] Therefore to retain the current one-memory-init-rules-them-all situation, revert this patch until another board emerges and will actually be pushed mainline that needs different setup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
* arm926ejs: add NXP LPC32x0 cpu series supportVladimir Zapolskiy2012-05-15-0/+379
| | | | | | | | This change adds initial support for NXP LPC32x0 SoC series. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* ARM926EJS: Fix cache.c to comply with checkpatch.plMarek Vasut2012-04-16-9/+8
| | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* ARM926EJS: Make asm routines volatile in cache opsMarek Vasut2012-04-16-1/+1
| | | | | | | | | | We certainly don't want the compiler to reorganise the code for dcache flushing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Stefano Babic <sbabic@denx.de>
* DMA: Split the APBH DMA init into block and channel initMarek Vasut2012-04-16-0/+6
| | | | | | | | | | | | | | | | | | | | | | | This fixes the issue where mxs_dma_init() was called either twice or never, without introducing any new init hooks. The idea is to allow each and every device using the APBH DMA block to configure and request only the channels it uses, instead of making it call init for all the channels as is now. The common DMA block init part, which only configures the block, is then called from CPUs arch_cpu_init() call. NOTE: This patch depends on: http://patchwork.ozlabs.org/patch/150957/ Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* ARM: 926ejs: use debug() for misaligned addressesStefano Babic2012-04-16-1/+1
| | | | | | | | | | | | Misaligned warnings are useful to debug faulty drivers. A misaligned warning is printed also when the driver is correct - use debug() instead of printf(). Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Albert Aribaud <albert.u.boot@aribaud.net> CC: Mike Frysinger <vapier@gentoo.org> CC: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
* arm: Use common .lds file where possibleSimon Glass2012-03-30-80/+0
| | | | | | | | | | Each cpu directory currently has its own .lds file. This is only needed in most cases because the start.o file is in a different subdir. Now that we can factor out this difference, we can move most cpus over to the common .lds file. Signed-off-by: Simon Glass <sjg@chromium.org>
* i.MX28: Enable caches by defaultMarek Vasut2012-03-29-0/+10
| | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* ARM926EJS: Implement cache operationsMarek Vasut2012-03-29-12/+54
| | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* nhk8815: fix build errorsAnatolij Gustschin2012-03-28-0/+10
| | | | | | | | | | | | | Fix: common/libcommon.o: In function `cread_line': /home/ag/git/u-boot/common/main.c:695: undefined reference to `get_ticks' /home/ag/git/u-boot/common/main.c:695: undefined reference to `get_tbclk' /home/ag/git/u-boot/common/main.c:698: undefined reference to `get_ticks' Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Alessandro Rubini <rubini@unipv.it> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Alessandro Rubini <rubini@unipv.it>
* i.MX28: Drop __naked function from spl_mem_initMarek Vasut2012-03-27-7/+3
| | | | | | | | | | | | | Instead of compiling the function and using the result as a constant, simply use the constant. NOTE: This patch works around bug: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52546 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
* i.MX28: Make the stabilization delays shorterMarek Vasut2012-03-27-4/+4
| | | | | | | | | | | | | Cut down the VDDIO/VDDA regulator stabilization delays to 500 uS. That should be enough according to the datasheet and bootlets. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Robert Deliën <robert@delien.nl> Cc: Fabio Estevam <festevam@gmail.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
* i.MX28: Enable additional DRAM address bitsMarek Vasut2012-03-27-1/+1
| | | | | | | | Enables all fourteen address lines for DRAM Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marek.vasut@gmail.com> Tested-by: Marek Vasut <marek.vasut@gmail.com>
* Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1 registersRobert Delien2012-03-26-57/+39
| | | | | | | | | This patch fixes erroneous 32-bit access to registers hw_clkctrl_frac0 and hw_clkctrl_frac1. Signed-off-by: Robert Delien <robert@delien.nl> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8Robert Delien2012-03-26-8/+8
| | | | | | | | | This patch renames mx28_register to mx28_register_32 in order to prepare for the introduction of an 8-bit register, mx28_register_8. Signed-off-by: Robert Delien <robert@delien.nl> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* i.MX28: Reformat the DRAM memory configuration dataMarek Vasut2012-03-26-38/+48
| | | | | | Reformat the data so it's easier to navigate through them. Signed-off-by: Marek Vasut <marex@denx.de>
* i.mx28: Replaced magic numbers for scratch register addresses with register ↵Robert Delien2012-03-26-8/+8
| | | | | | | | | definitions This patch replaces the use of magice numbers for scratch register addresses with earlier defined register definitions. Signed-off-by: Robert Delien <robert@delien.nl>
* ATMEL: remove old atmel_mci driverSven Schnelle2012-03-13-1/+1
| | | | | | | | All boards are using the gen_atmel_mci driver now, so no need to carry the old driver around. Signed-off-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Stop using builtin_run_command()Simon Glass2012-03-06-6/+1
| | | | | | | | | | Boards can select either the 'built-in' parser or the hush parser. We should not call builtin_run_command() if we are using the hush parser. We use run_command() instead, since it knows how to call the correct parser. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* Rename run_command() to builtin_run_command()Simon Glass2012-03-06-1/+1
| | | | | | | | | The current run_command() is only one of the parsing options - the other is hush. We should not call run_command() when the hush parser is being used. So we rename this function to better explain its purpose. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* dm6467Tevm: Use a common configuration file for davinci_dm6467evm and ↵prabhakar.csengg@gmail.com2012-02-27-1/+1
| | | | | | | | | | | | | | | | | | | | davinci_dm6467Tevm In commit 2d575e46859dd9127a9cec731ace77523e6ea2ab a separate header file was introduced for the DM6467T EVM, include/configs/davinci_dm6467Tevm.h. The substantial difference between the davinci_dm6467evm and the davinci_dm6467Tevm configuration is a single bit in the hardware revision that is passed to the Linux kernel and davinci_dm6467evm has REFCLK_FREQ = 27000000 where as davinci_dm6467Tevm.h has a REFCLK_FREQ = 33000000. This patch removes include/configs/davinci_dm6467Tevm.h. Instead the include/configs/davinci_dm6467evm.h configuration is used for DM6467T EVMs and renamed CFG_REFCLK_FREQ to CONFIG_REFCLK_FREQ and CONFIG_REFCLK_FREQ is defined in boards.cfg. Signed-off-by: Prabhakar Lad <prabhakar.csengg@gmail.com> Cc: Tom Rini <trini@ti.com>
* davinci: cleanup davinci_sync_env_enetaddr() fucntionHadli, Manjunath2012-02-27-3/+6
| | | | | | | | | | | | check for the return status for eth_getenv_enetaddr_by_index() and eth_setenv_enetaddr() functions and print appropriate message on failure. Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
* MX27: add missing get_tbclk()Stefano Babic2012-02-27-0/+5
| | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* MX28: Fix get_timer() / get_tbclk() issueMarek Vasut2012-02-27-2/+17
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
* mx28: fix SPL code to make USB booting workMatthias Fuchs2012-02-27-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes booting i.MX28 CPUs via USB download. In this mode the CPU's bootrom implements a USB HID device that accepts a bootstream. When downloading the bootstream via USB, first the SPL code is received and executed. Then the u-boot image is received and called. The USB bootmode is interrupt driven. This patch fixes two things: 1) The ARM's fast interrupt mode is disabled when the SPL code has been run. So save and restore the CPSR register. 2) Save and restore c1 control register: the exception vector location needs to be set back to bootrom space to make the USB interrupts work again. The SPL code needs to change this option for the ram size probing. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* i.MX28: Fix VDDIO and VDDA setupMarek Vasut2012-02-27-4/+12
| | | | | | | | | | | | The DC power STS shouldn't be checked if booting off 5V supply. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Robert Deliën <robert@delien.nl> Cc: Fabio Estevam <festevam@gmail.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
* Changes to move hawkboard to the new spl infrastructureSughosh Ganu2012-02-12-11/+17
| | | | | | | | | | | | | | | | | | This patch moves hawkboard to the new spl infrastructure from the older nand_spl one. Removed the hawkboard_nand_config build option -- The spl code now gets compiled with hawkboard_config, after building the main u-boot image, using the CONFIG_SPL_TEXT_BASE. Modified the README.hawkboard to reflect the same. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com> Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Christian Riesch <christian.riesch@omicron.at> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Christian Riesch <christian.riesch@omicron.at>
* arm, arm926ejs: Enable icache only if CONFIG_SYS_ICACHE_OFF is not definedChristian Riesch2012-02-12-1/+4
| | | | | | | | Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* arm, arm926ejs: Add option CONFIG_SYS_EXCEPTION_VECTORS_HIGHChristian Riesch2012-02-12-1/+6
| | | | | | | | | | | | | | The V bit of the c1 register of CP15 should not be cleared on DA850 SoCs since they have no valid memory at 0x00000000. This patch introduces a configuration option CONFIG_SYS_EXCEPTION_VECTORS_HIGH that allows setting the correct value for the V bit. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Reported-by: Sughosh Ganu <urwithsughosh@gmail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Sughosh Ganu <urwithsughosh@gmail.com> Cc: Heiko Schocher <hs@denx.de>
* arm, arm926ejs: Flush the data cache before disabling itSughosh Ganu2012-02-12-4/+8
| | | | | | | | | | | | | | | | | | | | | The current implementation invalidates the data cache before turning it off and causes problems on the hawkboard. See the discussion in http://lists.denx.de/pipermail/u-boot/2012-January/115212.html According to the ARM926EJ-S Technical Reference Manual, the cache should be flushed instead. Also fix the comments to match code. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com> Rebased and corrected commit message. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* arm, arm926ejs: Do cpu critical inits only for boards that require itChristian Riesch2012-02-12-2/+4
| | | | | | | | | | | | | | | | | This patch reverts commit ca4b55800ed74207c35271bf7335a092d4955416 "arm, arm926ejs: always do cpu critical inits" since it impacts all arm926ejs based configurations and caused problems, e.g., with the hawkboard. Instead the patch removes the CONFIG_SKIP_LOWLEVEL_INIT defines from the board configurations that need low level initialization. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* arm, davinci: Add lowlevel_init for SoCs other than DM644XChristian Riesch2012-02-12-0/+4
| | | | | | | | | | | | | The low level initialization code in arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S was written for DM644X SoCs only. This patch makes the lowlevel_init function in this file a dummy function for SoCs other than DM644X. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Tom Rini <trini@ti.com> Cc: Sergey Kubushyn <ksi@koi8.net> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
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