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* ARM: Various: Future-proof serial platdataAdam Ford2016-03-14-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A few boards still use ns16550_platdata structures, but assume the structure is going to be in a specific order. By explicitly naming each entry, this should also help 'future-proof' in the event the structure changes. Tested on the Logic PD Torpedo + Wireless. I only changed a handful of devices that used the same syntax as the Logic board. Appologies if I missed one or stepped on toes. Thanks to Derald Woods and Alexander Graf. Signed-off-by: Adam Ford <aford173@gmail.com> V6: Add fix to arch/arm/cpu/armv7/am33xx/board.c V5: Add fix to arch/arm/cpu/arm926ejs/lpc32xx/devices.c V4: Fix subject heading V3: Remove reg_offset out in all the structs. It was reverted out, and and if it did exist, it would get initialized to 0 by default. V2: I hastily copy-pasted the boards without looking at the UART number. This addresses 3 boards that use UART3 and not UART1. Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Use correct spelling of "U-Boot"Bin Meng2016-02-06-2/+2
| | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: lpc32xx: switch SPL builds to driver modelVladimir Zapolskiy2016-01-13-1/+1
| | | | | | | | | | | | | | | | For NXP LPC32xx boards the change enables SPL_DM option, this allows to use any driver model UART driver in SPL images, hence a restriction on HSUART in SPL image is removed and well as definitions for non-DM NS16550 driver, its DM version is used instead. Because SPL_DM requires malloc(), enable CONFIG_SPL_SYS_MALLOC_SIMPLE for LPC32xx boards. The change adds about 5KB to the resulting SPL image (for devkit3250 board SPL image is increased from 10672 to 15608 bytes). Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: lpc32xx: switch serial console to driver modelVladimir Zapolskiy2016-01-13-2/+35
| | | | | | | | | | | | | | | | | On NXP LPC32xx platform for non-SPL builds the change adds standard (NS16550) and high-speed UARTs to driver model. Due to specific of DM NS16550 device description UART clock can not be got in runtime and by default it is set to 13MHz, if board PERIPH_CLK is different, this should be specified in board configuration file. For SPL builds HSUARTs are disabled and non-DM NS16550 driver is compiled, if needed. The change also updates default configs of devkit3250 and work_92105 boards to reflect updates in platform files. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* lpc32xx: fix calculation of HCLK PLL output clockVladimir Zapolskiy2015-10-11-5/+5
| | | | | | | | Execution branches on feedback mode are swapped, this has no effect if default direct mode is on (then p_div is equal to 1 and Fout equals to Fcco), that's why the problem remained unnoticed for a long time. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* lpc32xx: remove duplicated DMA_CLK_ENABLE bit definitionVladimir Zapolskiy2015-09-11-2/+1
| | | | | | | | | | | | Because there is an originally defined CLK_DMA_ENABLE macro in clk.h, no reason to add another DMA_CLK_ENABLE macro with the same value. Remove DMA_CLK_ENABLE, since it does not follow naming convention from the code, this implies renaming of DMA_CLK_ENABLE to CLK_DMA_ENABLE in lpc32xx/devices.c file. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* usb: lpc32xx: add host USB driverSylvain Lemieux2015-08-18-0/+6
| | | | | | | | | | | | | Incorporate USB driver from legacy LPCLinux NXP BSP. The files taken from the legacy patch are: - lpc32xx USB driver - lpc3250 header file USB registers definition. The legacy driver was updated and clean-up as part of the integration with the latest u-boot. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Vladimir Zapolskiy <vz@mleia.com>
* dma: lpc32xx: add DMA driverSylvain Lemieux2015-08-18-0/+7
| | | | | | | | | | | | | Incorporate DMA driver from legacy LPCLinux NXP BSP. The files taken from the legacy patch are: - lpc32xx DMA driver - lpc3250 header file DMA registers definition. The legacy driver was updated and clean-up as part of the integration with the latest u-boot. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Vladimir Zapolskiy <vz@mleia.com>
* lpc32xx: cpu: add support for soft resetSylvain Lemieux2015-08-17-6/+17
| | | | | | | | Add support for optional soft reset (i.e. "RESOUT_N" not asserted during reset). To be compatible with the original U-Boot code, when the "addr" parameter is 0, a hard is performed; for any other values, a soft reset is done. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2015-08-13-1/+6
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| * net: lpc32xx: add RMII phy mode supportVladimir Zapolskiy2015-08-11-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LPC32xx MAC and clock control configuration requires some minor quirks to deal with a phy connected by RMII. It's worth to mention that the kernel and legacy BSP from NXP sets SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011 and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also in my tests an SMSC LAN8700 phy device connected over RMII seems to work correctly without touching this bit. Add support of RMII, if CONFIG_RMII is defined, this option is aligned with a number of boards, which already define the same config value. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* | nand: lpc32xx: add SLC NAND controller supportVladimir Zapolskiy2015-08-12-0/+6
|/ | | | | | | | | | | | | | | | | | | | | The change adds support of LPC32xx SLC NAND controller. LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips. This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned. Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine. The driver can be included to an SPL image. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* lpc32xx: add support for board work_92105Albert ARIBAUD \(3ADEV\)2015-04-10-0/+159
| | | | | | | | | | | | | | | | | | | | | | | Work_92105 from Work Microwave is an LPC3250- based board with the following features: - 64MB or 128MB SDR DRAM - 1 GB SLC NAND, managed through MLC controller. - Ethernet - Ethernet + PHY SMSC8710 - I2C: - EEPROM (24M01-compatible) - RTC (DS1374-compatible) - Temperature sensor (DS620) - DACs (2 x MAX518) - SPI (through SSP interface) - Port expander MAX6957 - LCD display (HD44780-compatible), controlled through the port expander and DACs This board has SPL support, and uses the LPC32XX boot image format. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* lpc32xx: add LPC32xx SSP support (SPI mode)Albert ARIBAUD \(3ADEV\)2015-04-10-0/+14
| | | | | Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* lpc32xx: add GPIO supportAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+5
| | | | | | This driver only supports Driver Model, not legacy model. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* lpc32xx: i2c: add LPC32xx I2C interface supportAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+11
| | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* lpc32xx: mtd: nand: add MLC NAND controllerAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+6
| | | | | | | | | | The controller's Reed-Solomon ECC hardware is used except of course for raw reads and writes. It covers in- and out-of-band data together. The SPL framework is supported. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* lpc32xx: add Ethernet supportAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+16
| | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* arm926ejs: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-22/+1
| | | | | | | | | | | | | | | | | Note1: In arch/arm/cpu/arm926ejs/spear/Makefile START := start.o was changed extra-$(CONFIG_SPL_BUILD) := start.o because spear/start.o is only used for SPL. Note2: START := start.o was missing from arch/arm/cpu/arm926ejs/mxs/Makefile. This commit simply adds extra-$(CONFIG_SPL_BUILD) := start.o Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-73/+5
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* arm926ejs: add NXP LPC32x0 cpu series supportVladimir Zapolskiy2012-05-15-0/+379
This change adds initial support for NXP LPC32x0 SoC series. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Marek Vasut <marek.vasut@gmail.com>
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