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* arm: socfpga: socrates: Remove Micrel PHY configurationMarek Vasut2015-12-20-47/+0
| | | | | | | | | | The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: sockit: Remove Micrel PHY configurationMarek Vasut2015-12-20-47/+0
| | | | | | | | | | The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: de0_nano: Remove Micrel PHY configurationMarek Vasut2015-12-20-53/+0
| | | | | | | | | | The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: cyclone5-socdk: Remove Micrel PHY configurationMarek Vasut2015-12-20-47/+0
| | | | | | | | | | The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: arria5-socdk: Remove Micrel PHY configurationMarek Vasut2015-12-20-47/+0
| | | | | | | | | | The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: socrates: Add missing PHY skew configMarek Vasut2015-12-20-0/+9
| | | | | | | | | Add missing KSZ9021 PHY skew configuration for the EBV socrates board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* net: phy: micrel: Configure KSZ9021/KSZ9031 skew from OFMarek Vasut2015-12-20-1/+145
| | | | | | | | | | | | | | | | Add code to process the KSZ9021/KSZ9031 OF props if they are present and configure skew registers based on the information from the OF. This code is only enabled if the DM support for ethernet is also enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> V2: - Implement struct ksz90x1_reg_field to describe the skew register fields more accurately. - Fix RXDV/TXEN skew register default value and offset.
* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-12-18-98/+12159
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| * microblaze: Do not handle watchdog and gpio in SPLMichal Simek2015-12-18-3/+6
| | | | | | | | | | | | watchdog and gpio are not validated for SPL that's why do not use them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * microblaze: Enable DM by defaultMichal Simek2015-12-18-1/+1
| | | | | | | | | | | | Enable DM for the whole architecture. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * microblaze: Enable OF_CONTROL by defaultMichal Simek2015-12-18-1/+1
| | | | | | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * microblaze: Remove support for LL_TEMACMichal Simek2015-12-18-46/+1
| | | | | | | | | | | | | | LL_TEMAC is available at big endian MB and it is not properly tested that's why the patch removes it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * microblaze: Use malloc setting via KconfigMichal Simek2015-12-18-6/+2
| | | | | | | | | | | | | | Clean board specific file. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * microblaze: Make room for malloc before ELFMichal Simek2015-12-18-1/+2
| | | | | | | | | | | | | | | | Create space below u-boot binary for early malloc. It means memory layout is stack grows down, space for early malloc, u-boot code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * dm: net: Fix DM for targets which use MANUAL_RELOCMichal Simek2015-12-18-0/+28
| | | | | | | | | | | | | | | | All ethernet operation needs to be updated for architectures which requires MANUAL_RELOC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: gem: Add driver dependencies to PHYLIBMichal Simek2015-12-18-15/+1
| | | | | | | | | | | | | | Clear driver dependecies via Kconfig. Remove PHYLIB dependency from the driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: gem: Fix typo in Kconfig entryMichal Simek2015-12-18-1/+1
| | | | | | | | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: gem: Separate recv and free_pkt functionsMichal Simek2015-12-18-20/+32
| | | | | | | | | | | | | | | | Use core to call net_process_received_packet() instead of call inside the driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: gem: Fix return value from recvMichal Simek2015-12-18-1/+1
| | | | | | | | | | | | | | | | recv function should return 0 instead of frame_len not to proceed the same packet again in core. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: gem: Setup default phy address to -1Michal Simek2015-12-18-1/+2
| | | | | | | | | | | | | | Undefined phy address is -1 not 0. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * arm: zynq: Update ZYBO config optionsNathan Rossi2015-12-18-0/+20
| | | | | | | | | | | | | | | | | | | | | | Update the ZYBO device tree and enable config options that relate to the added devices in the device tree. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <monstr@monstr.eu> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * spi: zynq_qspi: Add configuration to disable LQSPI featureNathan Rossi2015-12-18-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the Zynq Boot ROM code loads the payload from QSPI it uses the LQSPI feature of the QSPI device, however it does not clean up its configuration before handing over to the payload which leaves the device confgured to by-pass the standard non-linear operating mode. This ensures the Linear QSPI mode is disabled before re-enabling the device. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * tools: zynqimage: Clean up check_paramsNathan Rossi2015-12-18-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Clean up the param checking, removing some code paths that will never happen. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Tom Rini <trini@konsulko.com> Reported-by: Coverity (CID 133251) Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Add default ps7_init_gpl.c/h for ZYBONathan Rossi2015-12-18-1/+12046
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ps7_init_gpl.c/h for the ZYBO board. This instance of the ps7_init is generated by the Vivado 2015.3 tools using the system configuration provided by Digilent located on their website. Update the kconfig so that the defconfig is not overrided to use the custom init ps7_init_gpl target by default. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <monstr@monstr.eu> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Enable u-boot,dm-pre-reloc for sdhciMichal Simek2015-12-18-0/+6
| | | | | | | | | | | | | | | | Enable u-boot,dm-pre-reloc for sdhci for zc706, zed and zybo. And create aliases for it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2015-12-17-311/+380
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| * usb: kbd: don't use int xfers when polling via ctrl xfersStephen Warren2015-12-17-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP is enabled, use a GET_REPORT control transfer to retrieve the initial state of the keyboard. This matches the technique used to poll the keyboard state. This is useful since it eliminates the remaining use of interrupt transfers from the USB keyboard driver, which allows it to work with USB HCD that don't support interrupt transfers. Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * usb: add support of generic OHCI devicesAlexey Brodkin2015-12-17-0/+54
| | | | | | | | | | | | | | | | | | | | | | This driver is meant to be used with any OHCI-compatible host controller in case if there's no need for platform-specific glue such as setup of controller or PHY's power mode via GPIOs etc. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org> Cc: Marek Vasut <marex@denx.de>
| * usb: host: ehci: samsung: Move hcor initialization after usb phy setupLukasz Majewski2015-12-17-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | With the old order of initialization the hcor pointer has been setup to the same address as Exynos EHCI base address (0x12110000 instead of 0x12110010). Such behaviour was caused by reading value of 0 instead of 0x10 from EHCI HCCPBASE register without doing proper clock initialization before. To fix this problem hcor initialization has been moved after USB PHY setup. Now ehci_readl(&ctx->hcd->cr_capbase) returns correct value. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
| * usb: s3c-otg: Rename usb/s3c_udc.h to usb/dwc2_udc.hMarek Vasut2015-12-17-18/+18
| | | | | | | | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the global s3c_udc.h header to dwc2_udc.h. The rename is done automatically: $ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \ `git grep "s3c_udc\.h" | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Rename s3c_udc_probe() functionMarek Vasut2015-12-17-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch is the second and final to rename global symbol, the s3c_udc_probe() function. The rename is done automatically: $ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \ `git grep s3c_udc_probe | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Rename struct s3c_plat_otg_dataMarek Vasut2015-12-17-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch is the first to rename global symbol, the struct s3c_plat_otg_data. The rename is done automatically: $ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \ `git grep s3c_plat_otg_data | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Rename USB_GADGET_S3C_UDC_OTG* to USB_GADGET_DWC2_OTG*Marek Vasut2015-12-17-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | The s3c-otg IP block is in fact a DWC2 OTG one, so finally rename the config option to make it less misleading. No functional change, just a mechanical change done using the following script: git grep USB_GADGET_S3C_UDC_OTG | cut -d : -f 1 | sort -u | \ while read line ; do sed -i "s/USB_GADGET_S3C_UDC_OTG/USB_GADGET_DWC2_OTG/g" $line ; done Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Tweak the commentsMarek Vasut2015-12-17-5/+5
| | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. Tweak the comments in the driver to reflect this fact. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Rename remaining macrosMarek Vasut2015-12-17-22/+22
| | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the remaining S3C_* macros to match the DWC2 naming. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Rename sources to dwc2_*cMarek Vasut2015-12-17-6/+6
| | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the local source files to dwc2_*c and adjusts the Makefile to use the new names. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Rename local headers to dwc2_*hMarek Vasut2015-12-17-8/+8
| | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the local header files to dwc2_*h and adjusts the sources to use the new names. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Change the driver name to dwc2-udcMarek Vasut2015-12-17-3/+3
| | | | | | | | | | | | Just change the driver name. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Zap useless externsMarek Vasut2015-12-17-5/+3
| | | | | | | | | | | | | | The extern statements are useless, remove them. Also remove the extern ... controller, which is completely useless. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Rename remaining local s3c_*() functionsMarek Vasut2015-12-17-23/+23
| | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the remaining local s3c_*() functions to reflect this. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Rename s3c_udc_*() functionsMarek Vasut2015-12-17-47/+47
| | | | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the s3c_ep_*() functions to reflect this. The function s3c_udc_probe() is a special case and is not renamed by this patch yet. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Rename s3c_ep_*() functionsMarek Vasut2015-12-17-11/+11
| | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the s3c_ep_*() functions to reflect this. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Rename s3c_ep0_*() functionsMarek Vasut2015-12-17-14/+14
| | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the s3c_ep0_*() functions to reflect this. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Staticize functions in s3c_udc_otg_xfer_dma.cMarek Vasut2015-12-17-7/+7
| | | | | | | | | | | | Just staticize the functions, they are not used outside of the file. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Staticize s3c_udc_ep_set_stallMarek Vasut2015-12-17-3/+1
| | | | | | | | | | | | This function is local to s3c_udc_otg_xfer_dma.c , staticize it. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Rename struct s3c_requestMarek Vasut2015-12-17-28/+28
| | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_request to reflect this. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Rename struct s3c_epMarek Vasut2015-12-17-46/+46
| | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_ep to reflect this. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Rename struct s3c_dev_*_epMarek Vasut2015-12-17-4/+4
| | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_dev_*_ep to reflect this. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Rename struct s3c_usbotg_phy to dwc2_usbotg_phyMarek Vasut2015-12-17-5/+5
| | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames struct s3c_usbotg_phy to struct dwc2_usbotg_phy to make things more obvious and clear. Signed-off-by: Marek Vasut <marex@denx.de>
| * usb: s3c-otg: Split private bits from s3c_udc.hMarek Vasut2015-12-17-92/+108
| | | | | | | | | | | | | | | | | | Most of the functions are local to the s3c_udc driver, remove them from the s3c_udc.h header to stop those bits from propagating all over the place. Instead, move all the private stuff into new private s3c_udc_otg_priv.h header. Signed-off-by: Marek Vasut <marex@denx.de>
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