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* arm: dts: imx6ull: add pinctrl definesPeng Fan2016-10-04-0/+1024
| | | | | | | | | | Add pinctrl defines for NXP i.MX 6ULL. Since i.MX6ULL reuses some definitions of i.MX6UL, also add i.MX6UL pinctrl defines from linux kernel commit (29b4817d401). Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de>
* pinctrl: imx6: support i.MX6ULLPeng Fan2016-10-04-0/+5
| | | | | | | | | There two iomuxc for i.MX6ULL. one iomuxc is compatible is i.MX6UL, the other iomuxc is for SVNS usage, similar with the one in mx7. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Simon Glass <sjg@chromium.org>
* imx: iomux: fix snvs usage for i.MX6ULLPeng Fan2016-10-04-4/+14
| | | | | | | | | | | | SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module, not in IOMUXC, so correct the related registers' offset. Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate them from iomuxc pins. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com>
* imx: imx6ull: adjust the ldo 1.2v bandgap voltagePeng Fan2016-10-04-0/+7
| | | | | | | | | | Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0 bit[6:4]) setting to 2b'110. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: Add AIPS3 initializationPeng Fan2016-10-04-1/+1
| | | | | | | | Since the mx6ull adds the AIPS3, so enable its initialization. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: Update memory map addressPeng Fan2016-10-04-3/+14
| | | | | | | | Update memory map address for mx6ull. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: update clock settings and CCM register mapPeng Fan2016-10-04-29/+89
| | | | | | | | Update Clock settings and CCM register map for i.MX6ULL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: adjust POR_B setting for i.MX6ULLPeng Fan2016-10-04-0/+14
| | | | | | | | | | | | | | Adjust POR_B settings on i.MX6ULL according to IC design team's suggestion: 2'b00 : always PUP100K 2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL 2'b10 : always disable PUP100K 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: misc soc updatePeng Fan2016-10-04-4/+4
| | | | | | | | | | Update misc SOC related settings for i.MX6ULL, such as FEC mac address, cpu speed grading and mmdc channel mask clearing. Also update s_init to skip pfd reset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ul: using runtime check when configuring PMIC_STBY_REQPeng Fan2016-10-04-1/+1
| | | | | | | | | Since MX6ULL select MX6UL, we can not use IS_ENABLED(CONFIG_MX6UL) here, because this piece code is only for i.MX6UL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: skip setting ahb clockPeng Fan2016-10-04-1/+1
| | | | | | | | | Rom already initialized clock at 396M and 132M for arm core and ahb, so skip setting them again in U-Boot. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: timer: update gpt driver for i.MX6ULLPeng Fan2016-10-04-3/+4
| | | | | | | | | | The i.MX6ULL's GPT supportting taking OSC as clock source. Add i.MX6ULL support. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: ocotp: support i.MX6ULLPeng Fan2016-10-04-6/+46
| | | | | | | | | | | | | | | | | | | i.MX6ULL has two 128 bits fuse banks, bank 7 and bank 8, while other banks use 256 bits. So we have to adjust the word and bank index when accessing the bank 8. When in command line `fuse read 8 0 1`, you can image `fuse read 7 4 1` in the ocotp driver implementation for 6ULL. When programming, we use word index, so need to fix bank7/8 programming for i.mx6ull. For example: fuse prog 8 3 1; The word index is (8 << 3 | 3) --> 67. But actully it should be (7 << 3 | 7) ---> 63. So fix it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx-common: introduce is_mx6ullPeng Fan2016-10-04-0/+1
| | | | | | | Introduce is_mx6ull macro. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: add kconfig entry for MX6ULLYe Li2016-10-04-0/+4
| | | | | | | | | i.MX6ULL is derivative from i.MX6UL, so select MX6UL for MX6ULL. If need to differenate MX6ULL from MX6UL, use CONFIG_MX6ULL Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: add mx6ull major cpu typePeng Fan2016-10-04-1/+4
| | | | | | | | | Add i.MX6ULL major cpu type. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx6ull: add iomux header filePeng Fan2016-10-04-0/+1067
| | | | | | | | | Add iomux header file for i.MX6ULL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* README.imx6: Fix Boundary Devices nameFabio Estevam2016-10-04-1/+1
| | | | | | Correct name is "Boundary Devices". Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* board: tbs2910: Add CMD_PARTSoeren Moch2016-10-04-0/+2
| | | | | | | | | | There is no stable mmcblk device numbering over different linux versions. Enable CMD_PART to be able to query the UUID of the root filesystem partition. So we can pass root=PARTUUID=XXX instead of root=/dev/mmcblkXpY in bootargs. Leave the default environment as is for now to stay compatible with original TBS settings. Signed-off-by: Soeren Moch <smoch@web.de>
* imx_watchdog: Do not assert WDOG_B on watchdog initRoss Parker2016-10-04-1/+2
| | | | | | | | Currently the driver asserts WDOG_B by clearing WCR_WDA bit when enabling the watchdog. Do not clear WCR_WDA. Signed-off-by: Ross Parker <rossjparker@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: iomux-v3: fix pad setup on i.MX6DQP when CONFIG_MX6QDL is definedFilip Brozovic2016-10-04-1/+1
| | | | | | | | The CPU detection macro is_mx6dq returns 0 on an i.MX6DQP, so we need to check for it explicitly in order to correctly initialize the pads when CONFIG_MX6QDL is defined. Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
* board: tbs2910: Fix BOOTMAPSZSoeren Moch2016-10-04-1/+1
| | | | | | | | The linux kernel imx_v6_v7_defconfig sets the user/kernel memory split to 3G/1G now (was 2G/2G before). We have to adapt the BOOTMAPSZ so that the decompressor finds zImage and dtb in lowmem. Signed-off-by: Soeren Moch <smoch@web.de>
* mx6sabresd: Make SPL DDR configuration to match the DCD tableFabio Estevam2016-10-04-154/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | When using SPL on i.mx6 we frequently notice some DDR initialization mismatches between the SPL code and the non-SPL code. This causes stability issues like the ones reported at 7dbda25ecd6d7c ("mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang") and also: http://lists.denx.de/pipermail/u-boot/2016-September/266355.html . As the non-SPL code have been tested for long time and proves to be reliable, let's configure the DDR in the exact same way as the non-SPL case. The idea is simple: just use the DCD table and write directly to the DDR registers. Retrieved the DCD tables from: board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg and board/freescale/mx6sabresd/mx6qp.cfg (NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga) This method makes it easier for people converting from non-SPL to SPL code. Other benefit is that the SPL binary size is reduced from 44 kB to 39.9 kB. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* wandboard: Remove videoargs scriptFabio Estevam2016-10-04-26/+0
| | | | | | | | | | | | The videoargs script is kernel version dependent and since wandboard uses distro config, there is no need to handle videoargs locally. In case such video related settings are needed, then the proper location would be the distro extlinux.conf or boot.scr files. So remove 'videoargs' script. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* wandboard: Fix hang when going into low frequencyFabio Estevam2016-10-04-3/+3
| | | | | | | | | | | | | | A kernel hang is observed when running wandboard 3.14 kernel and going to the lowest operational point of cpufreq: # ifconfig eth0 down # echo 1 > /sys/class/graphics/fb0/blank The problem is caused by incorrect setting of the REFR field of register MDREF. Setting it to 4 refresh commands per refresh cycle fixes the hang. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* Prepare v2016.11-rc1Tom Rini2016-10-03-2/+2
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-10-03-205/+421
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| * rockchip: add boot-mode support for rk3288, rk3036Jacob Chen2016-10-01-20/+111
| | | | | | | | | | | | | | | | | | | | | | | | rockchip platform have a protocol to pass the the kernel reboot mode to bootloader by some special registers when system reboot. In bootloader we should read it and take action. We can only setup boot_mode in board_late_init becasue "setenv" need env setuped. So add CONFIG_BOARD_LATE_INIT to common header and use a entry "rk_board_late_init" to replace "board_late_init" in board file. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: move common function from board-file to rk3036-board.cJacob Chen2016-10-01-132/+84
| | | | | | | | | | | | | | To keep it same with 3288 Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rename board.c to rk3288-board.cJacob Chen2016-10-01-1/+1
| | | | | | | | | | Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: move partitons define from 3036-kylin to 3036-commonJacob Chen2016-10-01-24/+10
| | | | | | | | | | | | | | To keep it same with 3288. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: miniarm: remove eMMC supportXu Ziyuan2016-10-01-21/+6
| | | | | | | | | | | | | | The latest rk3288-miniarm board doesn't have eMMC device, so remove it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * config: evb-rk3399: enable pwm regulatorKever Yang2016-10-01-0/+1
| | | | | | | | | | | | | | Enable the pwm regulator for evb-rk3399. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dts: evb-rk3399: add init voltage node for vdd-centerKever Yang2016-10-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add a regulator-init-microvolt for vdd_center regulator so that we can get a init value for driver probe. Not like pmic regulator, the PWM regulator do not have a known default output value, so we would like to init the regulator when driver probe. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * Kconfig: rockchip: enable DM_PWM and DM_REGULATORKever Yang2016-10-01-0/+2
| | | | | | | | | | | | | | Enable DM_PWM and DM_REGULATOR on rockchip SoCs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: evb_rk3399: init vdd_center regulatorKever Yang2016-10-01-0/+6
| | | | | | | | | | | | | | | | Add vdd_center pwm regulator get_device to enable this regulator. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * power: regulator: add pwm regulatorKever Yang2016-10-01-0/+170
| | | | | | | | | | | | | | | | add driver support for pwm regulator. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rkpwm: fix the register sequenceKever Yang2016-10-01-1/+1
| | | | | | | | | | | | | | | | | | Reference to kernel source code, rockchip pwm has three type, we are using v2 for rk3288 and rk3399, so let's update the register to sync with pwm_data_v2 in kernel. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3399: update PPLL and pmu_pclk frequencyKever Yang2016-10-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update PPLL to 676MHz and PMU_PCLK to 48MHz, because: 1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz can not, 2. We think 48MHz is fast enough for pmu pclk and it is lower power cost than 99MHz, 3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using internally for kernel,it suppose not to change the bus clock like pmu_pclk in kernel, so we want to change it in uboot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: add usb mass storage feature support for rk3036jacob2.chen2016-10-01-0/+4
| | | | | | | | | | | | | | | | Enable ums feature for rk3036 boards, so that we can mount the mmc device to PC. Signed-off-by: jacob2.chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * Enable ROCKCHIP_SPL_BACK_TO_BROM for rock2 boardSandy Patterson2016-10-01-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Rock2 has been tested with back to brom feature. The tricky part is that with this feature the default environment is inside u-boot, and it's defined for every rk3288 board independetly. So I just changed it for rock2 here if ROCKCHIP_SPL_BACK_TO_BROM. Solve by moving environment after u-boot before 1M boundary Signed-off-by: Sandy Patterson <apatterson@sightlogix.com> Acked-by: Simon Glass <sjg@chromium.org>
| * Disable SPL_MMC_SUPPORT if ROCKCHIP_SPL_BACK_TO_BROM is enabled.Sandy Patterson2016-10-01-0/+3
| | | | | | | | | | | | | | | | Default SPL_MMC_SUPPORT to false when ROCKCHIP_SPL_BACK_TO_BROM is enabled. Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Signed-off-by: Sandy Patterson <apatterson@sightlogix.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: Fix SPL console output when ROCKCHIP_SPL_BACK_TO_BROM is enabledSandy Patterson2016-10-01-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move back_to_bootrom() call later in SPL init so that the console is initialized and printouts happen. Currently when ROCKCHIP_SPL_BACK_TO_BROM is enabled there is no console output from the SPL init stages. I wasn't sure exactly where this should happen, so if we are set to do run spl_board_init, then go back to bootrom there after preloader_console_init(). Otherwise fall back to old behavior of doing it in board_init_f. Signed-off-by: Sandy Patterson <apatterson@sightlogix.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: sdram: fix DDR address rangeXu Ziyuan2016-10-01-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The all current Rockchip SoCs supporting 4GB of ram have problems accessing the memory region 0xfe000000~0xff000000. Actually, some IP controller can't address to, so let's limit the available range. This patch fixes a bug which found in miniarm-rk3288-4GB board. The U-Boot was relocated to 0xfef72000, and .bss variants was also relocated, such as do_fat_read_at_block. Once eMMC controller transfer data to do_fat_read_at_block via DMA, DMAC can't access more than 0xfe000000. So that DMAC didn't work sane. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | ti_armv7_common: Disable Falcon Mode on HS devicesAndrew F. Davis2016-10-02-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | Authentication of images in Falcon Mode is not supported. Do not enable SPL_OS_BOOT when TI_SECURE_DEVICE is enabled. This prevents attempting to directly load kernel images which will fail, for security reasons, on HS devices, the board is locked if a non-authenticatable image load is attempted, so we disable attempting Falcon Mode. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
* | config: Remove usage of CONFIG_STORAGE_EMMCAndrew F. Davis2016-10-02-8/+0
| | | | | | | | | | | | | | | | | | This config option seems to be unused and is probably vestigial. Remove it. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ti: omap-common: Allow AM33xx devices to be built securelyAndrew F. Davis2016-10-02-1/+1
| | | | | | | | | | | | | | | | | | | | Like OMAP54xx and AM43xx family SoCs, AM33xx based SoCs have high security enabled models. Allow AM33xx devices to be built with HS Device Type Support. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
* | board: am33xx-hs: Allow post-processing of FIT image on AM33xxAndrew F. Davis2016-10-02-0/+8
| | | | | | | | | | | | | | | | | | | | | | When CONFIG_FIT_IMAGE_POST_PROCESS or CONFIG_SPL_FIT_IMAGE_POST_PROCESS is enabled board_fit_image_post_process will be called, add this function to am33xx boards when CONFIG_TI_SECURE_DEVICE is set to verify the loaded image. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
* | am33xx: config.mk: Fix option used to enable SPI SPL image typeAndrew F. Davis2016-10-02-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The option SPL_SPI_SUPPORT is used to enable support in SPL for loading images from SPI flash, it should not be used to determine the build type of the SPL image itself. The ability to read images from SPI flash does not imply the SPL will be booted from SPI flash. Unconditionally build SPI flash compatible SPL images. Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | doc: Update info on using AM33xx secure devices from TIAndrew F. Davis2016-10-02-0/+32
| | | | | | | | | | | | | | | | | | Add a section describing the additional boot types used on AM33xx secure devices. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
generated by cgit v1.1 at 2024-11-07 18:11:20 +0000