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| * dts: exynos: snow: Add memory layout descriptionSimon Glass2015-08-05-0/+53
| | | | | | | | | | | | | | Add a description of the snow memory layout to assist flashing tools which want to be able to deal with any exynos image. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: gpio: Check a GPIO is valid before using itSimon Glass2015-08-05-1/+5
| | | | | | | | | | | | | | | | | | Since a gpio_desc is allowed to be invalid we should return an error indicating that the operation cannot be completed. This can happen if the GPIO is optional - e.g. some devices may have a reset line and some may not. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Tidy up CPU frequency displaySimon Glass2015-08-05-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Line up the display with the line below, e.g.: CPU: Exynos5250 @ 1.7 GHz Model: Google Spring DRAM: 2 GiB MMC: EXYNOS DWMMC: 0 Also show the speed as GHz where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: video: Correct debug outputSimon Glass2015-08-05-2/+2
| | | | | | | | | | | | | | | | | | We should not print a message from the driver when the display is set up. This is normal behaviour. Change this message to use debug(). Also remove the double newline on another debug message. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Add support for the DisplayPort hotplug detectSimon Glass2015-08-05-0/+11
| | | | | | | | | | | | Allow this function to be selected using the pinmux API. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Correct return value in exynos_mmc_init()Simon Glass2015-08-05-1/+1
| | | | | | | | | | | | This function should return 0 on success, not 1. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: spi: Convert the timeout to debug()Simon Glass2015-08-05-3/+3
| | | | | | | | | | | | | | | | | | | | | | Since the timeout is reported through normal channels, and is sometimes expected (e.g. if the bus is being probed for a non-existent device), don't display the message in the driver. In general, drivers should not write to the console as this limits their usefulness in error conditions. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: video: Add support for the NXP PTN3460 bridgeSimon Glass2015-08-05-0/+48
| | | | | | | | | | | | | | | | | | This chip provides an eDP to LVDS bridge which is useful for SoCs that don't support LVDS displays (or it would waste scarce pins). There is no setup required by this chip, other than to adjust power-down and reset pins, and those are managed by the uclass. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: video: Add support for the Parade PS8622/625 bridgeSimon Glass2015-08-05-0/+178
| | | | | | | | | | | | | | | | This chip provides an eDP to LVDS bridge which is useful for SoCs that don't support LVDS displays (or it would waste scarce pins). The setup is included in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
| * video: Work around lack of pinctrlSimon Glass2015-08-05-10/+18
| | | | | | | | | | | | | | | | | | | | We haven't quite got pinctrl ready to apply to mainline. We don't want to GPIO pull-up/down support to the driver model GPIO layer either. So work around this for now. We can address this when pinctrl is complete. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: video: Add support for video bridgesSimon Glass2015-08-05-0/+223
| | | | | | | | | | | | | | | | | | A video bridge typically converts video from one format to another, e.g. DisplayPort to LVDS. Add driver model support for these with a simple interface to control activation and backlight. The uclass supports GPIO control of power and reset lines. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: pmic: Display the regulator limits on errorSimon Glass2015-08-05-1/+2
| | | | | | | | | | | | | | | | When a regulator command cannot honour the requested voltage, display the limits to try to be helpful. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * dm: power: Don't return an error when regulators are not autosetSimon Glass2015-08-05-1/+3
| | | | | | | | | | | | | | | | | | Not all regulators can be set up automatically. Adjust the code so that regulators_enable_boot_on() will return success when some are skipped. Only genuine errors are reported. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * dm: pmic: max77686: Support all BUCK regulatorsSimon Glass2015-08-05-8/+10
| | | | | | | | | | | | | | Add support for all BUCK regulators, now that the correct register is accessed for each. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: power: max77686: Correct BUCK register accessSimon Glass2015-08-05-3/+7
| | | | | | | | | | | | | | | | Some regulators use the wrong voltage register and thus it is not possible to control them. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * dm: pmic: Correct the pmic_reg_write() implementationSimon Glass2015-08-05-1/+1
| | | | | | | | | | | | | | This should write the register, not read it. Fix this bug. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * dm: pmic: max77686: Correct a few nitsSimon Glass2015-08-05-3/+3
| | | | | | | | | | | | | | | | The driver name should not have a space in it. Also the regulator names should match the case of the device tree. Fix these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * dm: power: Add support for S5M8767 regulatorsSimon Glass2015-08-05-0/+279
| | | | | | | | | | | | | | | | | | This PMIC is used with SoCs which need a combination of BUCKs and LDOs. The driver supports changing voltage and enabling/disabling each regulator. It supports the standard device tree binding and supports driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * dm: power: Add support for the S5M8767 PMICSimon Glass2015-08-05-0/+191
| | | | | | | | | | | | | | | | | | | | This PMIC is used with SoCs which need a combination of BUCKs and LDOs. The driver supports probing and basic register access. It supports the standard device tree binding and supports driver model. A regulator driver can be provided also. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * dm: power: Add support for TPS65090 FETsSimon Glass2015-08-05-0/+149
| | | | | | | | | | | | | | | | | | The TPS65090 has 7 FETs which are modelled as regulators. This allows them to be controlled by drivers easier, accessed through the 'regulator' command and used by other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * dm: power: Add a new driver for the TPS65090 PMICSimon Glass2015-08-05-0/+160
| | | | | | | | | | | | | | | | | | The existing TPS65090 driver does not support driver model. Add a new one that does. This can be used as a base for a regulator driver also. It uses the standard device tree binding. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * exynos: Enable the debug UART in SPLSimon Glass2015-08-05-0/+7
| | | | | | | | | | | | | | | | As a debugging aid, allow UART3 to be used as a debug UART in SPL. This is a precursor to proper UART support, which requires a substantial refactor. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: Add debug UART support for Samsung S5P serialSimon Glass2015-08-05-0/+32
| | | | | | | | | | | | | | Add a debug UART implementation for this serial driver. It does not set up pinmux automatically - this must be done before calling debug_uart_init(). Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: serial: Refactor init code for debug UARTSimon Glass2015-08-05-12/+24
| | | | | | | | | | | | | | | | | | The debug UART code needs to perform the same init as the normal UART driver. In preparation for this, move the init code into two functions, one for the basic init and one for setting the baud rate. This will make adding debug UART support easier. Signed-off-by: Simon Glass <sjg@chromium.org>
| * cros_ec: Support the LDO access method used by springSimon Glass2015-08-05-12/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver to support the special LDO access used by spring. This is a custom method in the cros_ec protocol - it does not use an I2C pass-through. There are two implementation choices: 1. Write a special LDO driver which can talk across the EC. Duplicate all the logic from TPS65090 for retrying when the LDO fails to come up. 2. Write a special I2C bus driver which pretends to be a TPS65090 and transfers reads and writes using the LDO message. Either is distasteful. The latter method is chosen since it results in less code duplication and a fairly simple (30-line) implementation of the core logic. The crosec 'ldo' subcommand could be removed (since i2c md/mw will work instead) but is retained as a convenience. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: cros_ec: Convert the I2C tunnel code to use driver modelSimon Glass2015-08-05-11/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Chrome OS EC supports tunnelling through to an I2C bus on the EC. This currently uses a copy of the I2C command code and a special 'crosec' sub-command. With driver model we can define an I2C bus which tunnels through to the EC, and use the normal 'i2c' command to access it. This simplifies the code and removes some duplication. Add an I2C driver which tunnels through to the EC. Adjust the EC code to support binding child devices so that it can be set up. Adjust the existing I2C xfer function to fit driver model better. For now the old code remains to allow things to still work. It will be removed in a later patch once the new flow is fully enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: dts: Support EC tunnel and main TPS65090 regulatorSimon Glass2015-08-05-48/+297
| | | | | | | | | | | | | | | | | | On pit and pi the TPS65090 regulator is connected only to the EC and we must use a tunnel to get to it. The existing U-Boot support relies on a special driver. Add a tunnel definition so that the new device-model TPS65090 driver can be used unmodified. Signed-off-by: Simon Glass <sjg@chromium.org>
| * exynos: dts: Add PMIC and regulator definitionsSimon Glass2015-08-05-0/+304
| | | | | | | | | | | | | | | | Snow and smdk5250 use a max77686 PMIC. We have a driver for this, so add the relevant node to the device tree so it can be used. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * exynos: dts: Sync up I2C ports with the kernelSimon Glass2015-08-05-89/+94
| | | | | | | | | | | | | | | | The kernel uses upper case for I2C unit addresses. Follow the same convention to reduce differences. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * exynos: i2c: Tidy up the driver model codeSimon Glass2015-08-05-36/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing driver model implementation uses the old non-driver-model code to operate, but has become impossibly tangled as a result. The actual algorithm is quite simple. Also the normal-speed and high-speed buses are quite different and it doesn't seem that useful to put them in the same driver. Finally, there is a bug which breaks communication with the Maxim sound codec and may cause problems with other device. Rewrite the driver model code for normal-speed operation so that it is easier to understand, and fix the bug. Add a TODO to split the drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
| * exynos: i2c: Fix code style with ReadWriteByte()Simon Glass2015-08-05-7/+7
| | | | | | | | | | | | | | | | This function should not use mixed case, and it is simpler to use clrbits_le32() when clearing bits. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * i2c: Add a mux for GPIO-based I2C bus arbitrationSimon Glass2015-08-05-0/+217
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While I2C supports multi-master buses this is difficult to get right. The implementation on the master side in software is quite complex. Clock-stretching and the arbitrary time that an I2C transaction can take make it difficult to share the bus fairly in the face of high traffic. When one or more masters can be reset independently part-way through a transaction it is hard to know the state of the bus. This driver provides a scheme based on two 'claim' GPIOs, one driven by the AP (Application Processor, meaning the main CPU) and one driven by the EC (Embedded Controller, a small CPU aimed at handling system tasks). With these they can communicate and reliably share the bus. This scheme has minimal overhead and involves very little code. It is used on snow to permit the EC and the AP to share access to the main system PMIC and battery. The scheme can survive reboots by either side without difficulty. This scheme has been tested in the field with millions of devices. Since U-Boot runs on the AP, the terminology used is 'our' claim GPIO, meaning the AP's, and 'their' claim GPIO, meaning the EC's. This terminology is used by the device tree bindings in Linux also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: i2c: Add support for multiplexed I2C busesSimon Glass2015-08-05-0/+316
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new I2C_MUX uclass. Devices in this class can multiplex between several I2C buses, selecting them one at a time for use by the system. The multiplexing mechanism is left to the driver to decide - it may be controlled by GPIOs, for example. The uclass supports only two methods: select() and deselect(). The current mux state is expected to be stored in the mux itself since it is the only thing that knows how to make things work. The mux can record the current state and then avoid switching unless it is necessary. So select() can be skipped if the mux is already in the correct state. Also deselect() can be made a nop if required. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: i2c: Add a function to transfer messagesSimon Glass2015-08-05-0/+24
| | | | | | | | | | | | | | | | | | | | | | Sometimes it is useful to be able to transfer a raw I2C message. This happens when the chip address needs to be set manually, or when the data to be sent/received is in another buffer. Add a function to provide access to this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * dm: i2c: Move definitions to the top of the header fileSimon Glass2015-08-05-43/+43
| | | | | | | | | | | | | | | | Move the flags and struct definitions higher in the file so that we can reference them with functions declared in the driver model section. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * dm: i2c: Correct comment nits in dm_i2c_reg_read/write()Simon Glass2015-08-05-0/+2
| | | | | | | | | | | | | | Add documentation for the @dev parameter. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * dm: i2c: Add a message debug functionSimon Glass2015-08-05-0/+26
| | | | | | | | | | | | | | Add a way to dump the contents of an I2C message for debugging purposes. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * dm: core: Support finding a device by phandleSimon Glass2015-08-05-0/+59
| | | | | | | | | | | | | | | | | | It is common for one node to reference another via a phandle. Add support for obtaining an attached device by this method. As an example, a node may have a 'power-supply' property which references a regulator, allowing the driver to turn on its power. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: usb: fix USB Ethernet without CONFIG_DM_ETH regressionMarcel Ziswiler2015-08-05-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following commit enforces CONFIG_DM_ETH for USB Ethernet which breaks any board using CONFIG_USB_HOST_ETHER without CONFIG_DM_ETH which this patch fixes. commit 69559093f6173dcfcb041df0995063bdbd07d49b dm: usb: Avoid using USB ethernet with CONFIG_DM_USB and no DM_ETH Tested on Colibri T20/T30 as well as Apalis T30 with CONFIG_USB_HOST_ETHER and CONFIG_USB_ETHER_ASIX enabled and a LevelOne USB-0301 ASIX AX88772 dongle. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ARM: tegra: Add p2371-0000 boardStephen Warren2015-08-06-0/+496
| | | | | | | | | | | | | | | | | | | | | | P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O board. The combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA, a GPIO expansion header, and an analog audio jack. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: Add e2220-1170 boardStephen Warren2015-08-06-0/+503
| | | | | | | | | | | | | | | | | | E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various expansion modules. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: p2571: remove another unused defineStephen Warren2015-08-06-3/+0
| | | | | | | | | | | | | | | | CONFIG_MAX77620_POWER isn't used anywhere. Don't define it in p2571.h. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: enable GPU DT node when appropriateAlexandre Courbot2015-08-06-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T124/210 requires some specific configuration (VPR setup) to be performed by the bootloader before the GPU can be used. For this reason, the GPU node in the device tree is disabled by default. This patch enables the node if U-boot has performed VPR configuration. Boards enabled by this patch are T124's Jetson TK1 and Venice2 and T210's P2571. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: move VPR configuration to a later stageAlexandre Courbot2015-08-06-18/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot is responsible for enabling the GPU DT node after all necessary configuration (VPR setup for T124) is performed. In order to be able to check whether this configuration has been performed right before booting the kernel, make it happen during board_init(). Also move VPR configuration into the more generic gpu.c file, which will also host other GPU-related functions, and let boards specify individually whether they need VPR setup or not. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: add comment re: autogeneration to pinmux headersStephen Warren2015-08-06-0/+32
| | | | | | | | | | | | | | | | | | | | Add a comment block to the top of each generated Tegra pinmux header file indicating that the file was auto-generated, should not be manually edited, and with a pointer to the tool and command used to generate it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: restrict usable RAM size furtherStephen Warren2015-08-06-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Additionally, ARM64 devices typically run a secure monitor in EL3 and U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3 code and data. These carve-outs are located at the top of 32-bit address space. Restrict U-Boot's RAM usage to well below the location of those carve-outs. Ideally, we would the secure monitor would inform U-Boot of exactly which RAM it could use at run-time. However, I'm not sure how to do that at present (and even if such a mechanism does exist, it would likely not be generic across all forms of secure monitor). Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra: P2571: Clean up config fileTom Warren2015-08-05-6/+1
| | | | | | | | | | | | | | Removed NS16550_COM1 #define, not used since there's no SPL for T210 Also changed the number of USB controllers to 1 as only USBD is used. Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra: spi: Move TEGRA114_SPI switch to defconfigsTom Warren2015-08-05-10/+5
| | | | | | | | | | | | | | | | | | | | | | All T114+ Tegra boards should be using the Kconfig TEGRA114_SPI switch. Remove it from include/config and put it into defconfig. Also removed unused TEGRA114_SPI_CTRLS from T114+ configs. All Tegra SoCs build OK with this change. Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.Tom Warren2015-08-05-174/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X. Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on T124/114/30/20. Thanks to Marcel Ziswiler for corrections to the T20/T30 values. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra: clocks: Add 38.4MHz OSC support for T210 useTom Warren2015-08-05-11/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs to be measured - should be close to 700MHz (1.4G/2). Note that some freqs aren't in the PLLU table in T210 TRM (13, 26MHz), so I used the 12MHz table entry for them. They shouldn't be selected since they're not viable T210 OSC freqs. Since there are now 2 new OSC defines, all tables (pll_x_table, PLLU) had to increase by two entries, but since 38.4/48MHz are not viable osc freqs on T20/30/114, etc, they're just set to 0. Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-10-10 19:17:28 +0000