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* | ARM: uniphier: drop unneeded defines related to legacy serial driverMasahiro Yamada2016-04-01-6/+0
| | | | | | | | | | | | | | These defined were used for pre-DM ns16550 serial driver. They are unneeded because UniPhier SoCs now use DM serial. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: dts: uniphier: add NAND pinmux nodeMasahiro Yamada2016-04-01-0/+5
| | | | | | | | | | | | This will be used to set up pin-muxing for the NAND controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: dts: uniphier: add clock-frequency to serial nodes of LD11/LD20Masahiro Yamada2016-04-01-0/+8
| | | | | | | | | | | | | | | | Since no clock driver is implemented for peripherals in U-Boot yet, this property is needed for the serial driver to set up the divisor register. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: support UniPhier PH1-LD11 pinctrl driverMasahiro Yamada2016-04-01-6/+7
| | | | | | | | | | | | | | | | The pinmux of PH1-LD11 is almost a subset of that of PH1-LD20 (as far as used in boot-loader), so this commit makes the driver shared between the two SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driverMasahiro Yamada2016-04-01-0/+120
| | | | | | | | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: support per-pin input enable for new SoCsMasahiro Yamada2016-04-01-1/+28
| | | | | | | | | | | | | | | | Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input signal gating for each pin. (While, existing ones only support it per pin-group.) This commit prepares the core part for that. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: introduce capability flagMasahiro Yamada2016-04-01-27/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core part of the UniPhier pinctrl driver needs to support a new capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens because pinctrl drivers include really SoC-specific stuff. This commit intends to tidy up SoC-specific parameters of the existing drivers before adding new ones. Having flags would be better than adding new members every time a new SoC-specific capability comes up. At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE. This capability (I'd say rather quirk) was added for PH1-Pro4 and PH1-Pro5 as requirement from our customer. For those SoCs, one pin-mux setting is controlled by the combination of two separate registers; the LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4). Because it is impossible to update two separate registers atomically, the LOAD_PINCTRL register should be set in order to make the pin-mux settings really effective. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | pinctrl: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-6/+3
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mmc: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-3/+6
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | gpio: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-5/+3
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | i2c: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-13/+10
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | clk: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-6/+3
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | serial: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-3/+5
| | | | | | | | | | | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: add sramupdate commandMasahiro Yamada2016-04-01-0/+4
| | | | | | | | | | | | This command would be useful to update U-Boot images in SRAM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: make u-boot-with-spl.bin really availableMasahiro Yamada2016-04-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | Commit d085ecd61b99 ("ARM: uniphier: switch to raw U-Boot image") claimed that u-boot-with-spl.bin would be useful in its commit log, but it was not available because the commit missed to define CONFIG_SPL_MAX_SIZE. Without it, CONFIG_SPL_PAD_TO is not defined either (see include/config_fallbacks.h). So, the SPL image is not padded correctly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mtd: nand: denali: max_banks calculation changed in revision 5.1Graham Moore2016-04-01-1/+12
|/ | | | | | | | | | | | | | Read Denali hardware revision number and use it to calculate max_banks, The encoding of max_banks changed in Denali revision 5.1. [ Linux commit : 271707b1d817f5104e02b2bd1bab43f0c8759418 ] Signed-off-by: Graham Moore <grmoore@opensource.altera.com> [Brian: parentheses around macro arg] Signed-off-by: Brian Norris <computersforpeace@gmail.com> [Masahiro: import from Linux and adjust ioread32() to readl() ] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-03-29-0/+2
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| * ARM: tegra210: set PLLE_PTS bit when enabling PLLEStephen Warren2016-03-29-0/+2
| | | | | | | | | | | | | | | | This bit needs to be set for system suspend/resume to work. This setting will be documented in an updated TRM at some time in the future. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-03-29-65/+440
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| * | armv8/ls2080ardb: Enable VID supportRai Harninder2016-03-29-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | This patch enable VID support for ls2080ardb platform. It uses the common VID driver. Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls1043aqds: dts: Set SPI mode for DSPIQianyu Gong2016-03-29-1/+7
| | | | | | | | | | | | | | | | | | | | | Clock phase and polarity for DSPI flash need to be set. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Add LS1023A SVRMingkai Hu2016-03-29-0/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Fix LS1043A SVR registerMingkai Hu2016-03-29-1/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | SECURE BOOT: Change fsl_secboot_validate func to pass image addrSaksham Jain2016-03-29-14/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use a pointer to pass image address to fsl_secboot_validate(), instead of using environmental variable "img_addr". Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | SECURE BOOT: Halt execution when secure boot failSaksham Jain2016-03-29-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of fatal failure during secure boot execution (e.g. header not found), reset is asserted to stop execution. If the RESET_REQ is not tied to HRESET, this allows the execution to continue. Add esbh_halt() after the reset to make sure execution stops. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | SECURE_BOOT: Use default bootargsSaksham Jain2016-03-29-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For secure boot, currently we were using fixed bootargs for all SoCs. This is not needed and we can use the bootargs which are used in non-secure boot. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | crypto/fsl: Make CAAM transactions cacheableSaksham Jain2016-03-29-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit solves CAAM coherency issue on ls2080. When caches are enabled and CAAM's DMA's AXI transcations are not made cacheable, Core reads/writes data from/to caches and CAAM does from main memory. This forces data flushes to synchronize various data structures. But even if any data in proximity of these structures is read by core, these structures again are fetched in caches. To avoid this problem, either all the data that CAAM accesses can be made cache line aligned or CAAM transcations can be made cacheable. So, this commit makes CAAM transcations as write back with write and read allocate. Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | crypto/fsl: Correct 64-bit write when MMU disabledSaksham Jain2016-03-29-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When MMU is disabled, 64-bit write must be aligned at 64-bit boundary. Becaue the memory location is not guaranteed to be 64-bit aligned, the 64-bit write needs to be split into two 32-bit writes to avoid the alignment exception. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-lsch3: Disable SMMU during secure bootSaksham Jain2016-03-29-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs to be put in bypass mode in uboot to enable CAAM transcations to pass through. For non-secure boot, SP BootROM doesn't enable SMMU, which is in bypass mode out of reset. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Add config for endianess of CCSR GURSaksham Jain2016-03-29-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GUR (DCFG) registers in CCSR space are in little endian format. Define a config CONFIG_SYS_FSL_CCSR_GUR_LE in arch/arm/include/asm/arch-fsl-layerscape/config.h Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Change env variable "fdt_high"Saksham Jain2016-03-29-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "fdt_high" env variable was set to 0xcfffffff for secure boot. Change it to 0xa0000000 for LS2080 to be consistent with non-secure boot targets. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-lsch3: Copy Bootscript and header from NOR to DDRSaksham Jain2016-03-29-7/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To unify steps for secure boot for xip (eg. NOR) and non-xip memories (eg. NAND, SD), bootscipts and its header are copied to main memory. Validation and execution are performed from there. For other ARM Platforms (ls1043 and ls1020), to avoid disruption of existing users, this copy step is not used for NOR boot. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Add bootscript header addr for secure bootSaksham Jain2016-03-29-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During secure boot, Linux image along with other images are validated using bootscript. This bootscript also needs to be validated before it executes. This requires a header for bootscript. When secure boot is enabled, default bootcmd is changed to first validate bootscript using the header and then execute the script. For ls2080, NOR memory map is different from other ARM SoCs. So a new address on NOR is used for this bootscript header (0x583920000). The Bootscript address is mentioned in this header along with addresses of other images. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080rdb: ls2080qds: Add secure boot supportSaksham Jain2016-03-29-4/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sec_init has been called at the beginning to initialize SEC Block (CAAM) which is used by secure boot validation later for both ls2080a qds and rdb. 64-bit address in ESBC Header has been enabled. Secure boot defconfigs are created for boards (NOR boot). Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-lsch3: Add new header for secure bootSaksham Jain2016-03-29-14/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For secure boot, a header is used to identify key table, signature and image address. A new header structure is added for lsch3. Currently key extension (IE) feature is not supported. Single key feature is not supported. Keys must be in table format. Hence, SRK (key table) must be present. Max key number has increase from 4 to 8. The 8th key is irrevocable. A new barker Code is used. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Add configs for SEC, SecMon, SRK and DCFGSaksham Jain2016-03-29-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add configs for various IPs used during secure boot. Add address and endianness for SEC and Security Monitor. SRK are fuses in SFP (fuses for public key's hash). These are stored in little endian format. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Add SFP Configs for LS2080Saksham Jain2016-03-29-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | In LS2080, SFP has version 3.4. It is in little endian. The base address is 0x01e80200. SFP is used in Secure Boot to read fuses. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | driver: net: fsl-mc: Check NULL before pointer dereferencePrabhakar Kushwaha2016-03-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NULL pointer should be checked before any dereference. This patch move memest after the NULL pointer check. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reported-by: Jose Rivera <german.rivera@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | driver: net: fsl-mc: Free dflt_dpio pointer after its usagePrabhakar Kushwaha2016-03-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Free dflt_dpio pointer after its usage during error handling Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reported-by: Jose Rivera <german.rivera@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Skip reconfigure QSPI clock when booting from QSPIQianyu Gong2016-03-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The qspi_cfg register is set by PBI when booting from QSPI. No need to changing it again. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls1043a: Update env settings for booting kernelQianyu Gong2016-03-24-4/+4
| | | | | | | | | | | | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080a: Update fdt path for fsl-mc nodeStuart Yoder2016-03-24-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fsl-mc node has been moved under /soc, so update the path references accordingly. Backwards compatibility is retained for /fsl-mc. Delete backwards compatibility for the completely obsolete /fsl,dprc@0. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | omap24xx_i2c: Implement CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOWGuy Thouret2016-03-28-0/+34
| | | | | | | | | | | | | | | Signed-off-by: Guy Thouret <guy.thouret@wems.co.uk> Cc: Heiko Schocher <hs@denx.de>
* | | dm: i2c: mxc_i2c: implement i2c_idle_busPeng Fan2016-03-28-9/+102
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement i2c_idle_bus in driver, then setup_i2c can be dropped for boards which enable DM_I2C/DM_GPIO/PINCTRL. The i2c_idle_bus force bus idle flow follows setup_i2c in arch/arm/imx-common/i2c-mxv7.c This patch is an implementation following linux kernel patch: " commit 1c4b6c3bcf30d0804db0d0647d8ebeb862c6f7e5 Author: Gao Pan <b54642@freescale.com> Date: Fri Oct 23 20:28:54 2015 +0800 i2c: imx: implement bus recovery Implement bus recovery methods for i2c-imx so we can recover from situations where SCL/SDA are stuck low. Once i2c bus SCL/SDA are stuck low during transfer, config the i2c pinctrl to gpio mode by calling pinctrl sleep set function, and then use GPIO to emulate the i2c protocol to send nine dummy clock to recover i2c device. After recovery, set i2c pinctrl to default group setting. " See Documentation/devicetree/bindings/i2c/i2c-imx.txt for detailed description. 1. Introuduce scl_gpio/sda_gpio/bus in mxc_i2c_bus. 2. Discard the __weak attribute for i2c_idle_bus and implement it, since we have pinctrl driver/driver model gpio driver. We can use device tree, but not let board code to do this. 3. gpio state for mxc_i2c is not a must, but it is recommended. If there is no gpio state, driver will give tips, but not fail. 4. The i2c controller was first probed, default pinctrl state will be used, so when need to use gpio function, need to do "pinctrl_select_state(dev, "gpio")" and after force bus idle, need to switch back "pinctrl_select_state(dev, "default")". This is example about how to use the gpio force bus idle function: " &i2c1 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; status = "okay"; [....] }; [.....] pinctrl_i2c1_gpio: i2c1grp_gpio { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 >; }; " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com>
* | Revert "pxa_lcd: make driver cache-aware"Tom Rini2016-03-27-16/+0
| | | | | | | | | | | | This reverts commit 59deb7fe8d23c8ec2b659d99323ec4a2ec19148a. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Revert "pxa_lcd: invert colors for Zipit Z2 to get white on black palette"Tom Rini2016-03-27-1/+1
| | | | | | | | | | | | This reverts commit 3bc8ffd9cb774feceefc7bdebe9353fcea071343. Signed-off-by: Tom Rini <trini@konsulko.com>
* | tools: env: bug: config structs must be defined in tools libraryAndreas Fenkart2016-03-27-4/+4
| | | | | | | | | | | | | | | | fw_senten/fw_printenv can be compiled as a tools library, excluding the fw_env_main object. Reported-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
* | ARM: asm: types: Introduce DMA_ADDR_T_64BITLokesh Vutla2016-03-27-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dma_addr_t holds any valid DMA address. If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32 bits wide. Bus addresses, e.g., PCI BARs, may be wider than 32 bits, but drivers do memory-mapped I/O to ioremapped kernel virtual addresses, so they don't care about the size of the actual bus addresses. Also 32 bit ARM systems with LPAE enabled can use 64bit address space, but DMA still use 32bit address like in case of DRA7 and Keystone platforms. This is inspired from the Linux kernel types implementation[1] [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/include/linux/types.h#n142 Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | efi_loader: Fix some entry/exit pointsAlexander Graf2016-03-27-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | When switching between EFI context and U-Boot context we need to swap the register that "gd" resides in. Some functions slipped through here, with efi_allocate_pool / efi_free_pool not doing the switch correctly and efi_return_handle switching too often. Fix them all up to make sure we always have consistent register state. Signed-off-by: Alexander Graf <agraf@suse.de>
* | cfi_flash: return device into read array mode after reading statusVasily Khoruzhick2016-03-27-0/+2
| | | | | | | | | | | | | | | | Otherwise flash remains in read status mode and it's not possible to access data on flash. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-11-09 14:35:21 +0000