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* video: tegra: Move to using simple-panel and pwm-backlightSimon Glass2016-07-05-335/+145
| | | | | | | | | | | | | | | | | | We have standard drivers for panels and backlights which can do most of the work for us. Move the tegra20 LCD driver over to use those instead of custom code. This patch includes device tree changes for the nvidia boards. I have only been able to test seaboard. If this patch is applied, these boards will also need to be synced with the kernel, and updated to use display-timings: - colibri - medcom-wide - paz00 - tec Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: dts: Sync tegra20 device tree files with LinuxSimon Glass2016-07-05-73/+2154
| | | | | | | | Sync everything except the display panel, which will come in a future patch. One USB port is left disabled since we don't want to support it in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* errno: Allow errno_str() to be used without CONFIG_ERRNO_STRSimon Glass2016-07-05-0/+5
| | | | | | | | | | | | The pmic framework uses errno_str() and this requires board that use it to enable CONFIG_ERRNO_STR to avoid a build error. Update the header to provide a NULL error message when CONFIG_ERRNO_STR is not defined, and fix the build error. This will show as "(null)" when U-Boot prints it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* errno: Add copyright header and header guardSimon Glass2016-07-05-0/+7
| | | | | | | | | Bring in a copyright for this file from cmd/pmic.c since this file was submitted by the same author at around the same time. Also fix the missing header guard. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* pci: tegra: actually program REFCLK_CFG* on recent SoCsStephen Warren2016-07-05-9/+10
| | | | | | | | | | | | | | | On recent SoCs, tegra_pcie_phy_enable() isn't called; but instead tegra_pcie_enable_controller() calls tegra_xusb_phy_enable(). However, part of tegra_pcie_phy_enable() needs to happen in all cases. Move that code to tegra_pcie_port_enable() instead. For reference, NVIDIA's downstream Linux kernel performs this operation in tegra_pcie_enable_rp_features(), which is called immediately after tegra_pcie_port_enable(). Since that function doesn't exist in the U-Boot driver, we'll just add it to the tail of tegra_pcie_port_enable() instead. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* pci: tegra: correctly program PADS_REFCLK registersStephen Warren2016-07-05-13/+9
| | | | | | | | | | | | | | | | The value that should be programmed into the PADS_REFCLK register varies per SoC. Fix the Tegra PCIe driver to program the correct values. Future SoCs will require different values in cfg0/1, so the two values are stored separately in the per-SoC data structures. For reference, the values are all documented in NV bug 1771116 comment 20. The Tegra210 value doesn't match the current TRM, but I've filed a bug to get the TRM fixed. Earlier TRMs don't document the value this register should contain, but the ASIC team has validated all these values, except for the Tegra20 value which is simply left unchanged in this patch. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge git://git.denx.de/u-boot-arcTom Rini2016-07-04-2/+4
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| * arc: make global_data.h usable in assembly filesAlexey Brodkin2016-07-04-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently on attempt to use global_data.h in an assembly file following will happen: -------------------->8----------------- ./arch/arc/include/asm/global_data.h: Assembler messages: ./arch/arc/include/asm/global_data.h:11: Error: bad instruction 'struct arch_global_data{' ./arch/arc/include/asm/global_data.h:12: Error: junk at end of line, first unrecognized character is `}' scripts/Makefile.build:316: recipe for target 'arch/arc/lib/start.o' failed -------------------->8----------------- In this change we disable struct arch_global_data in ASM which fixes the issue above. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * arc: Use "-mcpu=archs" instead of deprecated "-marchs" for ARC HSAlexey Brodkin2016-07-04-2/+2
| | | | | | | | | | | | | | | | | | Newer ARC toolchains don't support "-marchs" option any longer. Instead "-mcpu=archs" should be used. What's also important older toiolchains that support ARC HS cores will also happily accept "-mcpu=archs" so that's a very safe move. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-07-02-2/+396
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| * | sunxi: Add defconfig and DTS file for Allwinner R16 EVB (Parrot)Quentin Schulz2016-07-02-1/+393
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Parrot Board is an evaluation board with an Allwinner R16 (assumed to be close to an Allwinner A33), 4GB of eMMC, 512MB of RAM, USB host and OTG, a WiFi/Bluetooth combo chip, a micro SD Card reader, 2 controllable buttons, an LVDS port with separated backlight and capacitive touch panel ports, an audio/microphone jack, a camera CSI port, 2 sets of 22 GPIOs and an accelerometer. The DTS file is identical to the one submitted to the upstream kernel. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add missing boot_media fields in the SPL headerOlliver Schinagl2016-07-02-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit b19236fd1 ("sunxi: Increase SPL header size to 64 bytes to avoid code corruption") Added defines for MMC0 and SPI as boot identification. After verifying on an OLinuXino Lime2 with NAND and eMMC, the expected values have been confirmed and added to spl.h Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: spl: Fix DRAM info printingHans de Goede2016-07-02-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | The switch to simple_printf was causing the SPL dram info to show as: DRAM: u MiB This fixes this by switching from %lu to %d for printing the DRAM size. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-07-01-4/+9
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| * | ehci: mx7: fix otg id detectionPeng Fan2016-06-25-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USBNC_PHYCFG2_ACAENB bit should be cleared to enable the OTG ID detection, not set it. When the bit is set, the ACA Resistance Detection is enabled, which disables the OTG ID detection, because the internal pull up is off. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | ehci: mx7: fix usbnc_regsPeng Fan2016-06-25-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | There is a 4 bytes hole between phy_cfg2 and phy_status, fix the usbnc_regs structure to include the hole. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * | usb: fsl: Fix NULL terminating issue for usb controller name stringRajesh Bhagat2016-06-25-1/+2
| | | | | | | | | | | | | | | | | | | | | Fixes NULL terminating issue for usb controller name string by using sizeof operator. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-07-01-1/+1
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| * | arm: socfpga: Fix "improve raw MMC SPL boot"Marek Vasut2016-06-23-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | This fixes commit d31e9c575f24f4b7f5f382ccae70d7a86bbc379d , which broke booting from SD card on all SoCFPGA boards. The patch assumes the bootloader partition to be partition 3, at the end of the SD card, which doesn't make any sense. U-Boot assumes the bootloader partition is partition 1 or that the bootloader image is at offset +1 MiB from the start of SD card. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Sylvain Lesne <lesne@alse-fr.com>
* | Prepare v2016.07-rc3Tom Rini2016-07-01-1/+1
| | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-07-01-454/+714
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| * | ARM: uniphier: add external IRQ setup codeMasahiro Yamada2016-07-02-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | I will carry this work-around until it is cared in the kernel. This looks up the AIDET node and sets up a register to handle active low interrupt signals. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: dts: uniphier: add AIDET nodesMasahiro Yamada2016-07-02-0/+40
| | | | | | | | | | | | | | | | | | | | | The AIDET (ARM Interrupt Detector Add-on Circuit) is a kind of syscon block related with the interrupt controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add Ethernet pin-mux settingsMasahiro Yamada2016-07-02-0/+94
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: avoid building unneeded pin-mux tables for SPLMasahiro Yamada2016-07-02-171/+192
| | | | | | | | | | | | | | | | | | | | | SPL does not use all of the devices, so we can save some memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: support pin configuration for dedicated pinsMasahiro Yamada2016-07-02-154/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration (pin biasing, drive strength control), but not pin-muxing. Allow to fill the mux value table with -1 for those pins; pins with mux value -1 will be skipped in the pin-mux set function. The mux value type should be changed from "unsigned" to "int" in order to accommodate -1 as a special case. [ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: split pinctrl driver for PH1-LD11 and PH1-LD20Masahiro Yamada2016-07-02-8/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PH1-LD11 and PH1-LD20 have much pin controlling in common, so I added a single driver shared between them in the initial commit. However, the Ethernet pin-mux settings I am going to add are different with each other, and they may diverge more as the progress of development. Split it into two dedicated drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: allow to have pinctrl node under syscon nodeMasahiro Yamada2016-07-02-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the UniPhier pinctrl driver itself is a syscon, but it turned out much more reasonable to make it a child node of a syscon because our syscon node consists of a bunch of system configuration registers, not only pinctrl, but also phy, and misc registers. It is difficult to split the node. This commit allows to migrate to the new DT structure. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: dts: uniphier: sync Device Trees with upstream LinuxMasahiro Yamada2016-07-02-138/+99
| | | | | | | | | | | | | | | | | | I periodically sync Device Trees for better maintainability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: remove unneeded pin group nand_cs1Masahiro Yamada2016-06-30-3/+0
| | | | | | | | | | | | | | | | | | | | | This SoC does not support NAND CS1. This place-holder is no longer necessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: fix NAND pin-mux setting for PH1-LD11/LD20Masahiro Yamada2016-06-30-2/+2
| | | | | | | | | | | | | | | | | | My mistake in the initial support patch. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: remove wrong pin-mux functions for ProXstream2Masahiro Yamada2016-06-30-2/+0
| | | | | | | | | | | | | | | | | | These are pin group names, not function names. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: fix typo "talbe"Masahiro Yamada2016-06-30-1/+1
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | mmc: increase MMC SDHCI read status timeoutSteve Rae2016-07-01-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise, ocassionally see errors like this: Flashing sparse image at offset 2078720 Flashing Sparse Image sdhci_send_command: Timeout for status update! mmc fail to send stop cmd write_sparse_image: Write failed, block #2181088 [0] This does not affect the actual writing speed, which is controlled by the default value: CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT It only increases the retries when reading: SDHCI_INT_STATUS to avoid the timeout error. Signed-off-by: Steve Rae <steve.rae@raedomain.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | ti_omap5_common: Find right dtb file for DRA72-RevC EvmLokesh Vutla2016-07-01-3/+9
| | | | | | | | | | | | | | | | | | DRA72-Evm revC uses dra72-evm-revc.dtb. Update the same in env vatiables. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | autoboot: move bootdelay >= 0 check to abortboot()Masahiro Yamada2016-07-01-14/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the bootdelay >= 0 check to the caller, which simplifies the callees. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | autoboot: move CONFIG_SILENT_CONSOLE handlingMasahiro Yamada2016-07-01-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Factor out the same code from the callees to the caller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | autoboot: rename abortboot_{keyed, normal} to __abortbootMasahiro Yamada2016-07-01-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because abortboot_keyed() and abortboot_normal() are not compiled at the same time, we can rename both of them to __abortboot(). This allows to drop #ifdef from the caller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | autoboot: remove CONFIG_ZERO_BOOTDELAY_CHECKMasahiro Yamada2016-07-01-93/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the help message of CONFIG_BOOTDELAY says, CONFIG_BOOTDELAY=-2 means the autoboot with no delay, with no abort check even if CONFIG_ZERO_BOOTDELAY_CHECK is defined. To sum up, the autoboot behaves as follows: [1] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=y autoboot with no delay, but you can abort it by key input [2] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n autoboot with no delay, with no check for abort [3] CONFIG_BOOTDELAY=-1 disable autoboot [4] CONFIG_BOOTDELAY=-2 autoboot with no delay, with no check for abort As you notice, [2] and [4] come to the same result, which means we do not need CONFIG_ZERO_BOOTDELAY_CHECK. We can control all the cases only by CONFIG_BOOTDELAY, like this: [1] CONFIG_BOOTDELAY=0 autoboot with no delay, but you can abort it by key input [2] CONFIG_BOOTDELAY=-1 disable autoboot [3] CONFIG_BOOTDELAY=-2 autoboot with no delay, with no check for abort This commit converts the logic as follow: CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n --> CONFIG_BOOTDELAY=-2 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Christian Riesch <christian.riesch@omicronenergy.com> Acked-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
* | | doc: bootdelay: drop explanation about CONFIG_BOOTDELAY from READMEMasahiro Yamada2016-07-01-17/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The same information now exists in common/Kconfig. Do not duplicate documentation from the point of view of maintainability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* | | ARM: socfpga: move CONFIG_BOOTDELAY to Kconfig for IS1 boardMasahiro Yamada2016-07-01-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This recently added board missed the tree-wide migration of CONFIG_BOOTDELAY. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
* | | ARM: AM437x: Align HS device variant defconfig filenameAndreas Dannenberg2016-07-01-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align the name of the defconfig file for high-security (HS) device variants from the AM43xx family of SoCs with the corresponding name used for the general purpose devices. This allows for easier cross-association of those files and also provides room to grow from an HS device part number perspective. Furthermore, update and cleanup associated MAINTAINERS file. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Madan Srinivas <madans@ti.com>
* | | driver: qspi: correct QSPI disable CS reset valuePraneeth Bajjuri2016-07-01-1/+1
|/ / | | | | | | | | | | | | | | | | | | | | Correcting QSPI disable/unselect CS reset value. CTRL_CORE_CONTROL_IO_2: QSPI_MEMMAPPED_CS[10:8] This is not causing any issue, but its better to untouch the reserved bits. Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com>
* | x86: coreboot: Remove the dummy pch driverBin Meng2016-06-29-27/+0
| | | | | | | | | | | | | | | | | | There is a dummy pch driver in the coreboot directory. This causes drivers of its children fail to function due to empty ops. Remove the whole file since it is no longer needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-06-28-151/+94
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| * | armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIsAbhimanyu Saini2016-06-28-105/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently layescape SoCs are not using cpu nodes. So removing them in favour of compatibly with similar SoCs that have different cores like LS2080A and LS2088A. This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCsPrabhakar Kushwaha2016-06-28-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs. like LS2080A, LS1043A, LS1012A. So append "A" to SoC names. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | mmc: fsl: introduce wp_enablePeng Fan2016-06-28-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introudce wp_enable. To check WPSPL, wp_enable needs to be set to 1 in board code. Take i.MX6UL for example, for some boards, they do not use WP singal, so they does not configure USDHC1_WP_SELECT_INPUT, and its default value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and SION bit set. So USDHC controller can always get wp signal and WPSPL shows write protect and blocks driver continuing. This is not what we want to see, so add wp_enable, and if set to 0, just omit the WPSPL checking and this does not effect normal working of usdhc controller. If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | fsl_esdhc: Update clock enable bits for USDHCYe Li2016-06-28-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN, HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec register. The driver uses RSTA to replace the clock gate off operation. But this is not a good solution because: 1. when using RSTA, we should wait this bit to clear by itself. This is not implemeneted in the code. 2. After RSTA is set, it is recommended that the Host Driver reset the external card and reinitialize it. So in this patch, we change to use the vendorspec registers for these bits operation. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | mmc: fsl: reset to normal boot mode when eMMC fast bootPeng Fan2016-06-28-9/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting in eMMC fast boot, MMC host does not exit from boot mode after bootrom loading image. So the first command 'CMD0' sent in uboot will pull down the CMD line to low and cause errors. This patch cleans the MMC boot register in "mmc_init" to put the MMC host back to normal mode. Also clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-11-09 22:54:55 +0000