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* strider: Add DP501 support for cpu modelDirk Eibach2016-03-21-26/+59
| | | | | Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-03-20-11/+26
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| * arm: socfpga: sr1500: Misc updates (SPI speed, env location)Stefan Roese2016-03-20-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes the following changes to the SR1500 board port: - Update defconfig to support SPI NOR (use make savedefconfig). - Increase SPI speed to a maximum of 100MHz for faster system bootup. - Change environment location, so that its not between SPL and main U-Boot. This way the combined SPL / U-Boot image can be used for updates. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de>
| * arm: socfpga: Allow boards to define a custom environment sizeStefan Roese2016-03-20-0/+2
| | | | | | | | | | | | | | | | | | | | This patch makes it possible that boards can define a board-specific env size. This is used by the SR1500 SoCFPGA board port. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Marek Vasut <marex@denx.de>
| * arm: socfpga: Fix SR1500 env positionMarek Vasut2016-03-20-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the inclusion of the common socfpga configuration file further down in the sr1500 configuration, so that the socfpga_common.h can check if environment is in SPI NOR and it's location is defined and if it is not, define default location. This fixes "arm: socfpga: Enabling U-Boot environment support in QSPI" which introduced a minor warning. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de>
| * arm: socfpga: Enabling U-Boot environment support in QSPIChin Liang See2016-03-20-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Enabling the support of storing U-Boot environment within serial NOR flash. By default, its still store into SDMMC Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de>
* | usb: xhci: Fix vendor command error if the request type is ↵Ted Chen2016-03-20-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | USB_REQ_SET_ADDRESS or USB_REQ_SET_CONFIGURATION. Add test into xhci_submit_control_message for usb requesttype in USB vendor request being of standardized type. This fixes detection of certain USB fixes, for example Ethernet, USB 3.0 port. Non standardized requesttype in USB vendor request will be ignored. Signed-off-by: Ted Chen <tedchen@realtek.com> Tested-by: Anand Moon <linux.amoon@gmail.com>
* | usb: Change power-on / scanning timeout handlingStefan Roese2016-03-20-94/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the USB port scanning procedure and timeout handling in the following ways: a) The power-on delay in usb_hub_power_on() is now reduced to a value of max(100ms, "hub->desc.bPwrOn2PwrGood * 2"). The code does not wait using mdelay, instead usb_hub_power_on() will wait before querying the device in the scanning loop later. The total timeout for this hub, which is 1 second + "hub->desc.bPwrOn2PwrGood * 2" is calculated and will be used in the following per-port scanning loop as the timeout to detect active USB devices on this hub. b) Don't delay the minimum delay (for power to stabilize) in usb_hub_power_on(). Instead skip querying these devices in the scannig loop until the delay time is reached. c) The ports are now scanned in a quasi parallel way. The current code did wait for each (unconnected) port to reach its timeout and only then continue with the next port. This patch now changes this to scan all ports of all USB hubs quasi simultaneously. For this, all ports are added to a scanning list. This list is scanned until all ports are ready by either a) reaching the connection timeout (calculated earlier), or by b) detecting a USB device. This results in a faster USB scan time as the recursive scanning of USB hubs connected to the hub that's currently being scanned will start earlier. One small functional change to the original code is, that ports with overcurrent detection will now get rescanned multiple times (PORT_OVERCURRENT_MAX_SCAN_COUNT). Without this patch: starting USB... USB0: USB EHCI 1.00 scanning bus 0 for devices... 9 USB Device(s) found time: 20.163 seconds With this patch: starting USB... USB0: USB EHCI 1.00 scanning bus 0 for devices... 9 USB Device(s) found time: 1.822 seconds So ~18.3 seconds of USB scanning time reduction. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* | usb: Don't reset the USB hub a 2nd timeStefan Roese2016-03-20-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Debugging has shown, that all USB hubs are being reset twice while USB scanning. This introduces additional delays and makes USB scanning even more slow. Testing has shown that this 2nd USB hub reset doesn't seem to be necessary. This patch now removes this 2nd USB hub reset. Resulting in faster USB scan time. Here the current numbers: Without this patch: => time usb start starting USB... USB0: USB EHCI 1.00 scanning bus 0 for devices... 9 USB Device(s) found time: 24.003 seconds With this patch: => time usb start starting USB... USB0: USB EHCI 1.00 scanning bus 0 for devices... 9 USB Device(s) found time: 20.392 seconds So ~3.6 seconds of USB scanning time reduction. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Stephen Warren <swarren@nvidia.com> Cc: Marek Vasut <marex@denx.de>
* | usb: Remove 200 ms delay in usb_hub_port_connect_change()Stefan Roese2016-03-20-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes 2 mdelay(200) calls from usb_hub_port_connect_change(). These delays don't seem to be necessary. At least not in my tests. Here the number for a custom x86 Bay Trail board (not in mainline yet) with a quite large and complex USB hub infrastructure. Without this patch: starting USB... USB0: USB EHCI 1.00 scanning bus 0 for devices... 9 USB Device(s) found time: 28.415 seconds With this patch: starting USB... USB0: USB EHCI 1.00 scanning bus 0 for devices... 9 USB Device(s) found time: 24.003 seconds So ~4.5 seconds of USB scanning time reduction. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Stephen Warren <swarren@nvidia.com> Cc: Marek Vasut <marex@denx.de>
* | usb: legacy_hub_port_reset(): Speedup hub reset handlingStefan Roese2016-03-20-2/+7
|/ | | | | | | | | | | | | | | | | | Start with a short USB hub reset delay of 20ms. This can be enough for some configurations. The 2nd delay at the end of the loop is completely removed. Since the delay hasn't been long enough, a longer delay time of 200ms is assigned and will be used in the next loop round. This hub reset handling is also used in the v4.4 Linux USB driver, hub_port_reset(). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Stephen Warren <swarren@nvidia.com> Cc: Marek Vasut <marex@denx.de>
* dm: blk: Add tests for block devicesSimon Glass2016-03-17-0/+97
| | | | | | | Add some tests to check that block devices work as expected. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: sandbox: Drop the pre-DM host implementationSimon Glass2016-03-17-90/+0
| | | | | | | | Driver model is used for host device block devices now, so we don't need the old code. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: sandbox: Switch over to use DM for block devicesSimon Glass2016-03-17-0/+1
| | | | | | | | Now that the drivers used by sandbox support CONFIG_BLK, we can switch sandbox over to use driver model for block devices. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: usb: Unbind old block devices when shutting down USBSimon Glass2016-03-17-1/+5
| | | | | | | | | | | | | | | | | When 'usb start' is used, block devices are created for any USB flash sticks and disks, etc. When 'usb stop' is used, these block devices are currently not removed. We don't want old block devices hanging around since they can still be visible to U-Boot. Therefore, when USB is shut down, remove and unbind all the block devices created by the USB subsystem. Possibly we should unbind all devices which don't cause problems by being unbound. Most likely we can remove everything except USB controllers, hubs and emulators. We can consider that later. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* buildman: Clarify the use of -VSimon Glass2016-03-17-2/+3
| | | | | | | | | This option outputs to the log file, not to the terminal. Clarify that in the help, and add a mention of it in the README. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* buildman: Add a way to specific a full toolchain prefixSimon Glass2016-03-17-110/+226
| | | | | | | | | | | | | | | | At present buildman allows you to specify the directory containing the toolchain, but not the actual toolchain prefix. If there are multiple toolchains in a single directory, this can be inconvenient. Add a new 'toolchain-prefix' setting to the settings file, which allows the full prefix (or path to the C compiler) to be specified. Update the documentation to match. Suggested-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* buildman: Allow branch names which conflict with directoriesSimon Glass2016-03-17-0/+7
| | | | | | | | | | At present if you try to use buildman with the branch 'test' it will complain that it is unsure whether you mean the branch or the directory. This is a feature of the 'git log' command that buildman uses. Fix it by resolving the ambiguity. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* dm: ns16550: Add support for reg-offset propertyMichal Simek2016-03-17-2/+5
| | | | | | | | | | | | reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Moved the new field to the end of the struct to avoid problems: Signed-off-by: Simon Glass <sjg@chromium.org>
* Revert "fdt: fix address cell count checking in fdt_translate_address()"Przemyslaw Marczak2016-03-17-3/+4
| | | | | | | | | | | | | | | | | | | This reverts commit 71105f50fedddfa5b0535d102c3d5078671721ad. The reverted commit was applied for a temporary to unbreak few Exynos boards on the release. After the discussion about the change, this commit should be avoided. Fixed device-tree for Exynos, allows reverting it without any issues. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* dts:exynos:update pinctrl size-cells and fix child regsPrzemyslaw Marczak2016-03-17-29/+29
| | | | | | | | | | | | | | | | | | | This change is required to avoid warnings about invalid size-cells defined in device-tree pinctrl nodes for Exynos. Tested on: - Odroid U3 - Odroid XU3 Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* gpio: Report errors when GPIOs cannot be readSimon Glass2016-03-17-7/+27
| | | | | | | Some controllers do not allow the output value to be read. Detect this and report the error in that case. Signed-off-by: Simon Glass <sjg@chromium.org>
* cmd_dhry.c: Use lldiv for vax_mips calculation as wellTom Rini2016-03-17-1/+1
| | | | | | | | | | Since dhry_per_sec is a u64 we must also use lldiv here when working with it. Otherwise: ../lib/dhry/cmd_dhry.c:(.text.do_dhry+0xd8): undefined reference to `__udivdi3' On some platforms. Signed-off-by: Tom Rini <trini@konsulko.com>
* x86: Add congatec conga-QA3/E3845-4G (Bay Trail) supportStefan Roese2016-03-17-0/+506
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM, installed on the congatec Qseven 2.0 evaluation carrier board (conga-QEVAL). Its port is very similar to the MinnowboardMAX port and also uses the Intel FSP as described in doc/README.x86. Currently supported are the following interfaces / devices: - UART (via Winbond legacy SuperIO chip on carrier board) - Ethernet (PCIe Intel I210 / E1000) - SPI including SPI NOR as boot-device - USB 2.0 - SATA via U-Boot SCSI IF - eMMC - Video (HDMI output @ 800x600) - PCIe Not supported yet is: - I2C - USB 3.0 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for the samus chromebookSimon Glass2016-03-17-1/+876
| | | | | | | | | | | | | | | | | | | | | | | This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support a chained-boot development flowSimon Glass2016-03-17-0/+80
| | | | | | | | | | | | | | | | | | Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI without any 16-bit init. This can help during development by allowing U-Boot to avoid doing all the init required by the platform. U-Boot expects its GDT to be set up correctly by its 16-bit code. If coreboot doesn't do this (because it hasn't run the payload setup code yet) then this won't happen. In this case we cannot rely on the GDT settings. U-Boot will hang or crash if these are wrong. Provide a development-only option to set up the GDT correctly. This is just a hack so you can jump to U-Boot from any stage of coreboot, not just at the end. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dts: Drop memory SPD compatible stringSimon Glass2016-03-17-3/+0
| | | | | | | | This is not needed now that the memory controller driver has the SPD data in its own node. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert to use the common SDRAM codeSimon Glass2016-03-17-311/+83
| | | | | | | Adjust the existing implementation to use the new common SDRAM init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add common SDRAM-init codeSimon Glass2016-03-17-0/+327
| | | | | | | | | The code to call the memory reference code is common to several Intel CPUs. Add common code for performing this init. Intel calls this 'Pre-EFI-Init' (PEI), where EFI stands for Extensible Firmware Interface. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move common PCH code into a common placeSimon Glass2016-03-17-84/+99
| | | | | | | | The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dhry: Correct dhrystone calculation for fast machinesSimon Glass2016-03-17-3/+5
| | | | | | | At present samus reports about 5600 DMIPS. With the default iteration count this is OK, but if 10 million runs are performed it overflows. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Add a 64-bit division routine to the private librarySimon Glass2016-03-17-1/+247
| | | | | | | | | | | | This is missing, with causes lldiv() to fail on boards with use the private libgcc. Add the missing routine. Code is available for using the CLZ instruction but it is not enabled at present. This comes from coreboot version 4.0. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fix a header nit in x86-chromebook.hSimon Glass2016-03-17-1/+0
| | | | | | | There is an extra line in the comment in the header. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a function to set the IOAPIC IDSimon Glass2016-03-17-0/+18
| | | | | | | Add a function to set the ID in the IOAPIC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update README for new developmentsSimon Glass2016-03-17-3/+13
| | | | | | | Update a few points which have become out-of-date. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use white on black for the console on chromebooksSimon Glass2016-03-17-0/+2
| | | | | | | | This is a little easier on the eyes, particularly when the backlight is set to maximum. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a default address for reference codeSimon Glass2016-03-17-0/+2
| | | | | | | | Add an address which can be used for loading and running the reference code when needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add video supportSimon Glass2016-03-17-1/+1174
| | | | | | | | | | | | | | Add a video driver for Intel's broadwell integrated graphics controller. This uses a binary blob for most init, with the driver just performing a few basic tasks. This driver supports VESA as the mode-setting mechanism. Since most boards don't support driver model yet with VESA, a special case is added to the Kconfig for broadwell. Eventually all boards will use driver model and this can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add support for high-speed I/O lane with MESimon Glass2016-03-17-0/+58
| | | | | | | | Provide a way to determine the HSIO (high-speed I/O) version supported by the Intel Management Engine (ME) implementation on the platform. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add a GPIO driverSimon Glass2016-03-17-0/+208
| | | | | | | Add a GPIO driver for the GPIO peripheral found on broadwell devices. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add support for SDRAM setupSimon Glass2016-03-17-0/+509
| | | | | | | | | Broadwell uses a binary blob called the memory reference code (MRC) to start up its SDRAM. This is similar to ivybridge so we can mostly use common code for running this blob. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add power-control supportSimon Glass2016-03-17-0/+220
| | | | | | | | | | Broadwell requires quite a bit of power-management setup. Add code to set this up correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598373/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add reference code supportSimon Glass2016-03-17-0/+114
| | | | | | | | Broadwell needs a special binary blob to set up the PCH. Add code to run this on start-up. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add an LPC driverSimon Glass2016-03-17-0/+110
| | | | | | | | Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly uses common code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add a northbridge driverSimon Glass2016-03-17-0/+60
| | | | | | | | Add a driver for the broadwell northbridge. This sets up the location of several blocks of registers. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add a SATA driverSimon Glass2016-03-17-0/+270
| | | | | | | | Add a SATA driver for broadwell. This supports connecting an SSD and the usual U-Boot commands to read and write data. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add a pinctrl driverSimon Glass2016-03-17-0/+590
| | | | | | | | | | | GPIO pins need to be set up on start-up. Add a driver to provide this, configured from the device tree. The binding is slightly different from the existing ICH6 binding, since that is quite verbose. The new binding should be just as extensible. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: broadwell: Add a PCH driverSimon Glass2016-03-17-0/+839
| | | | | | | Add a driver for the broadwell low-power platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add basic support for broadwellSimon Glass2016-03-17-0/+1246
| | | | | | | | This adds the broadwell architecture, with the CPU driver and some useful header files. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dts: Update the pinctrl binding a littleSimon Glass2016-03-17-10/+11
| | | | | | | Make a few minor updates to make the meaning clearer. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-10 01:11:55 +0000