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* s5pc1xx: update cache routinesMinkyu Kang2010-01-13-23/+130
| | | | | | | | | | Because of v7_flush_dcache_all is moved to omap3/cache.S and s5pc110 needs cache routines, update s5pc1xx cache routines. l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S and invalidate_dcache is modified for SoC specific. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* samsung: fix DMC1_MEM_CFG for s3c64xxSeunghyeon Rhee2009-12-04-2/+2
| | | | | | | | | | | | | | | The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit memory bus and there is no need to control CKE for each chip separately. AFAIK, CKE1 is not at all connected. Only CKE0 is used. Futhermore, it should be '0' always for S3C6410. When tested with a board which has a S3C6410 and the same memory configuration, a side effect is observed that u-boot command "reset" doesn't work leading to system hang. Leaving the bit clear is safe in most cases. Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Add a unified s3c24x0 header filekevin.morfitt@fearnside-systems.co.uk2009-11-20-95/+87
| | | | | | | | | | This patch adds a unified s3c24x0 cpu header file that selects the header file for the specific s3c24x0 cpu from the SOC and CPU configs defined in board config file. This removes the current chain of s3c24-type #ifdef's from the s3c24x0 code. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* S3C6400/SMDK6400: fix stack_setup in start.SSeunghyeon Rhee2009-11-13-8/+1
| | | | | | | | | | | | | Fix stack_setup to place the stack on the correct address in DRAM accroding to U-Boot standard and remove conditional compilation by CONFIG_MEMORY_UPPER_CODE macro that is not necessry. This macro was introduced and used only by this board for some unclear reason. The definition of this macro is also removed because it's not referenced elsewhere. Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com> Tested-by: Minkyu Kang <mk7.kang@samsung.com>
* s5pc1xx: serial: fix the error check logicMinkyu Kang2009-11-13-7/+17
| | | | | | | Because of Frame error, Parity error and Overrun error are occured only receive operation, need to masking when error checking. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Clean-up of s3c24x0 header fileskevin.morfitt@fearnside-systems.co.uk2009-11-10-461/+490
| | | | | | | | | | | | | | Cleans up the s3c24x0 header files: s4c24x0.h: removes the use of 'volatile' from the S3C24X0_REG8, S3C24X0_REG16 and S3C24X0_REG32 register typedef's. Registers are always accessed using the IO accessor functions which cast the register address as 'volatile' anyway so it isn't required here. s3c2400.h and s3c2410.h: insert a blank line between the static inline functions Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
* Merge branch 'master' of git://git.denx.de/u-boot-armMinkyu Kang2009-11-10-755/+7937
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| * Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-10-31-69/+54
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| | * sh: Update lowlevel_init.S of espt-gigaNobuhiro Iwamatsu2009-10-30-9/+1
| | | | | | | | | | | | | | | | | | | | | There was the point that did not use write macro. Change to write macro. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | * sh: Move some defs to convince 'pcrel too far'Nobuhiro Iwamatsu2009-10-30-54/+53
| | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Takashi Yoshii <yoshii.takashi@gmail.com>
| | * sh: Remove malloc_bin_reloc from lib_sh, lib_nios2 and lib_nios.Nobuhiro Iwamatsu2009-10-30-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | By "arm/microblaze/nios/nios2/sh: Remove relocation fixups" (commit: 0630535e2d062dd73c1ceca5c6125c86d1127a49", doesn't need malloc_bin_reloc function. This commit remove this. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sbc8349: fix incorrect commentWolfgang Denk2009-10-28-1/+1
| |/ | | | | | | | | | | | | | | The comment for the BR0_PRELIM port size initialization incorrectly stated 32 bit, while it's actually 16 bit. The code is correct. Reported-by: Guenter Koellner <guenter.koellner@nsn.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-boot-cfi-flashWolfgang Denk2009-10-28-133/+175
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| | * cfi: Add weak default function for flash_cmd_reset()Stefan Roese2009-10-28-133/+175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the CFI driver issues both AMD and Intel reset commands. This is because the driver doesn't know yet which chips are connected. This dual reset seems to cause problems with the M29W128G chips as reported by Richard Retanubun. This patch now introduces a weak default function for the CFI reset command, still with both resets. This can be overridden by a board specific version if necessary. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-sparcWolfgang Denk2009-10-28-2/+2
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| | * | Fix bug in jumptable call stubs for SPARC.Sergey Mironov2009-10-27-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Sergey Mironov <ierton@gmail.com> Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | | Fix Compliation warning for TNY-A9260 and TNY-A9G20Sandeep Paulraj2009-10-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch fixes a compilation warning by defining CONFIG_SYS_64BIT_VSPRINTF in the config file Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | Fix Compliation warning for SBC35-A9G20 boardSandeep Paulraj2009-10-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch fixes a compilation warning by defining CONFIG_SYS_64BIT_VSPRINTF in the config file Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | galaxy5200: Add default environment variablesEric Millbrandt2009-10-28-2/+8
| | |/ | |/| | | | | | | | | | | | | | | | Extend bootdelay to 10 seconds. Set boot retry time to 120 seconds and use reset to retry. Define default bootcommand and bootargs for production. Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
| * | Coding Style cleanup; update CHANGELOG, prepare -rc1v2009.11-rc1Wolfgang Denk2009-10-28-56/+6210
| | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | Add 'editenv' commandPeter Tyser2009-10-27-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | The editenv command can be used to edit an environment variable. Editing an environment variable is useful when one wants to tweak an existing variable, for example fix a typo or change the baudrate in the 'bootargs' environment variable. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * | setenv(): Delete 0-length environment variablesPeter Tyser2009-10-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously setenv() would only delete an environment variable if it was passed a NULL string pointer as a value. It should also delete an environment variable when it encounters a valid string pointer of 0-length. This change/fix is generally useful and is necessary for the upcoming "editenv" command. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * | readline(): Add ability to modify a string bufferPeter Tyser2009-10-27-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the 'buf' parameter is a non-0-length string, its contents will be edited. Previously, the initial contents of 'buf' were ignored and the user entered its contents from scratch. This change is necessary to support the upcoming "editenv" command but could also be used for future commands which require a user to modify an existing string. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * | cread_line(): Remove unused variablesPeter Tyser2009-10-27-4/+1
| | | | | | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * | Check for NULL prompt in readline_into_buffer()Peter Tyser2009-10-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, passing readline() or readline_into_buffer() a NULL 'prompt' parameter would result in puts() printing garbage when CONFIG_CMDLINE_EDITING was enabled. Note that no board currently triggers this bug. Enabling CONFIG_CMDLINE_EDITING on some boards (eg bab7xx) would result in the bug appearing. This change is only intended to prevent someone from running into this issue in the future. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
| * | drivers/net/phy/miiphybb.c: fix warning: no newline at end of fileWolfgang Denk2009-10-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add missing newline. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Luigi Mantellini <luigi.mantellini@idf-hit.com> Cc: Ben Warren <biggerbadderben@gmail.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-10-27-81/+460
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| | * | mpc85xx: Configure QE USB for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setup QE pin multiplexing for USB function, configure needed BCSRs and add some fdt fixups. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | mpc85xx: Configure QE UART for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-21/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make QE UART usable by Linux we should setup pin multiplexing and turn UCC2 Ethernet node into UCC2 QE UART node. Also, QE UART is mutually exclusive with UART0, so we can't enable it if eSDHC is in 4-bits mode on pilot boards, or if it's a prototype board with eSDHC in 1- or 4-bits mode. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | mpc85xx: Setup QE pinmux for SPI Flash on MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI Flash (M25P40) is connected to the SPI1 bus, we need a few qe_iop entries to actually enable SPI1 on these boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | mpc85xx: Setup SRIO memory region LAW for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch sets memory window for Serial RapidIO on MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | mpc85xx: Add eLBC NAND support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-19/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simply add some defines, and adjust TLBe setup to include some space for eLBC NAND. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-1/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | xpedite5370: Enable multi-core supportPeter Tyser2009-10-27-4/+17
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | 85xx: MP Boot Page Translation updatePeter Tyser2009-10-27-31/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | ppc/85xx/pci: fsl_pci_init: pcie agent mode supportVivek Mahajan2009-10-27-13/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally written by Jason Jin and Mingkai Hu for mpc8536. When QorIQ based board is configured as a PCIe agent, then unlock/enable inbound PCI configuration cycles and init a 4K inbound memory window; so that a PCIe host can access the PCIe agents SDRAM at address 0x0 * Supported in fsl_pci_init_port() after adding pcie_ep as a param * Revamped copyright in drivers/pci/fsl_pci_init.c * Mods in 85xx based board specific pci init after this change Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | 85xx/p1_p2_rdb: Fixing DDR configuration for 800MHz data ratePoonam Aggrwal2009-10-27-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | 85xx/p1_p2rdb: Fix crash while configuring 32 bit DDR i/f for P1020RDB.Poonam Aggrwal2009-10-27-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The data being modified was in NOR flash which caused the crash. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | fdt_support: Add multi-serial support for stdout fixupAnton Vorontsov2009-10-26-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently fdt_fixup_stdout() is using hard-coded CONFIG_CONS_INDEX constant. With multi-serial support, the CONS_INDEX may no longer represent actual console, so we should try to extract port number from the current stdio device name instead of always hard-coding the constant value. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Gerald Van Baren <vanbaren@cideas.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | ppc/85xx: Fix crashes due to generation of SPE instructionLeon Woestenberg2009-10-26-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot crashed on the last instruction: int parse_stream_outer(struct in_str *inp, int flag) { effa4784: 94 21 ff 38 stwu r1,-200(r1) effa4788: 7c 08 02 a6 mflr r0 effa478c: 42 9f 00 05 bcl- 20,4*cr7+so,effa4790 <parse_stream_outer+0xc> effa4790: 7d 80 00 26 mfcr r12 effa4794: 13 c1 b3 21 evstdd r30,176(r1) ...which is a SPE instruction, although -mno-spe was used. tmp/cross/ppce500v2/bin/powerpc-angstrom-linux-gnuspe-gcc --version powerpc-angstrom-linux-gnuspe-gcc (GCC) 4.3.3 Seems to be a known issue (since 2008-04?!) Googled some, turns out this patch/workaround works for me on MPC8536DS. See http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html for more info Signed-off-by: Leon Woestenberg <leon@sidebranch.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | ppc/85xx: Make L2 support more robustDave Liu2009-10-26-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According the user manual, we need loop-check the L2 enable bit set. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | ppc/85xx: Fix compiler warning in nand_spl/.../p1_p2_rdb/nand_boot.cKumar Gala2009-10-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_boot.c: In function 'board_init_f': nand_boot.c:44: warning: 'sys_clk' may be used uninitialized in this function Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | ppc/85xx: Fix building NAND_SPL out of treeKumar Gala2009-10-26-0/+12
| | |/ | | | | | | | | | | | | | | | | | | We need to source files to exist in the O=<FOO> nand_spl dir when we build out of tree. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | Revert "env: only build env_embedded and envcrc when needed"Wolfgang Denk2009-10-27-13/+27
| |/ | | | | | | | | | | Breaks building on many boards, and no really clean fix available yet. This reverts commit 6dab6add2d8ee80905234b326abc3de11be1d178.
| * License cleanup: Fix license header for some esd display configurationsMatthias Fuchs2009-10-24-44/+102
| | | | | | | | | | | | | | | | | | | | | | These files were autogenerated by EPSON configuration tools. This patch replaces the autogenerated file headers by the GPL license notice. This change is done with the explicit permission of Epson Research & Development / IC Software Development. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
| * sf: add GPL-2 license infoMike Frysinger2009-10-24-0/+4
| | | | | | | | | | | | | | Some of the new spi flash files were missing explicit license lines. Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| * fdt: Fix fdt padding issue for initrd mem_rsvKumar Gala2009-10-24-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Its possible that we end up with a device tree that happens to be a particular size that after we call fdt_resize() we don't have any space left for the initrd mem_rsv. Fix this be adding a second mem_rsv into the size calculation. We had one to cover the fdt itself and we have the potential of adding a second for the initrd. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
| * Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-10-24-2460/+6322
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| | * Merge branch 'master-sync' of git://git.denx.de/u-boot-armWolfgang Denk2009-10-24-2460/+6322
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| * | \ Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-10-24-241/+317
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