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| | * x86: bios: Synchronize stack between real and protected modeJian Luo2015-07-14-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | PCI option rom may use different SS during its execution, so it is not safe to assume esp pointed to the same location in the protected mode. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * video: vesa_fb: Look up VGA device by class instead of idBin Meng2015-07-14-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Per PCI spec, VGA device reports its class as standard 030000h in its configuration space, so we can use it to determine if we need run option rom instead of testing the supported vendor/device ids. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * dm: pci: Correct bus number when scanning sub-busesSimon Glass2015-07-14-1/+1
| | | | | | | | | | | | | | | | | | | | | The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it so that sub-buses are numbered correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * dm: pci: Use the correct hose when configuring devicesSimon Glass2015-07-14-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * x86: queensbay: Change PCIe root ports' interrupt routingBin Meng2015-07-14-10/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far interrupt routing works pretty well for any on-chip devices on Intel Crown Bay. When inserting any PCIe card to any PCIe slot, Linux kernel is smart enough to do interrupt swizzling and figure out device's irq using its parent bridge's interrupt routing info all the way up to its root port. In U-Boot all PCIe root ports' interrupts were routed to PIRQ E/F/G/H before, while actually all PCIe downstream ports received INTx are routed to PIRQ A/B/C/D directly and not configurable. Now we change this mapping so that any external PCIe device can work correctly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: crownbay: Enable writing MP tableBin Meng2015-07-14-0/+1
| | | | | | | | | | | | | | | | | | | | | Enable writing MP table for Intel Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Update README.x86 for SMP supportBin Meng2015-07-14-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Document U-Boot multi-processor support as well as configuration tables like SFI and MP tables for SMP OS kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Generate a valid MultiProcessor (MP) tableBin Meng2015-07-14-0/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement write_mp_table() to create a minimal working MP table. This includes an MP floating table, a configuration table header and all of the 5 base configuration table entries. The I/O interrupt assignment table entry is created based on the same information used in the creation of PIRQ routing table from device tree. A check duplicated entry logic is applied to prevent writing multiple I/O interrupt entries with the same information. Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we need actually write the MP table at the F seg, just like we did for PIRQ routing and SFI tables. With MP table existence, linux kernel will switch to I/O APIC and local APIC to process all the peripheral interrupts instead of 8259 PICs. This takes full advantage of the multicore hardware and the SMP kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Add MultiProcessor (MP) table APIsBin Meng2015-07-14-0/+688
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MP table provides a way for the operating system to support for symmetric multiprocessing as well as symmetric I/O interrupt handling with the local APIC and I/O APIC. We provide a bunch of APIs for U-Boot to write the floating table, configuration table header as well as base and extended table entries. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Remove inline for lapic access routinesBin Meng2015-07-14-151/+153
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove inline for lapic access routines and expose lapic_read() & lapic_write() as APIs to read/write lapic registers. Also move stop_this_cpu() to mp_init.c as it has nothing to do with lapic. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Add I/O APIC register access routinesBin Meng2015-07-14-1/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | I/O APIC registers are addressed indirectly. Add io_apic_read() and io_apic_write() routines to help register access. Two macros for I/O APIC ID and version register offset are also added. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Clean up ioapic header fileBin Meng2015-07-14-23/+3
| | | | | | | | | | | | | | | | | | | | | Remove all the dead/unused macros from asm/ioapic.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Reduce PIRQ routing table sizeBin Meng2015-07-14-9/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to populate multiple irq info entries with the same bus number and device number, but with different interrupt pin. We can use the same entry to store all the 4 interrupt pin (INT A/B/C/D) routing information to reduce the whole PIRQ routing table size. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Ignore function number when writing PIRQ routing tableBin Meng2015-07-14-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In fill_irq_info() pci device's function number is written into the table, however this is not really necessary. The function number can be anything as OS doesn't care about this field, neither does the PIRQ routing specification. Change to always writing 0 as the function number. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Write correct bus number for the irq routerBin Meng2015-07-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | We should write correct bus number to the PIRQ routing table for the irq router from device tree, instead of hard-coded zero. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: queensbay: Correct Topcliff device irqsBin Meng2015-07-14-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are 4 usb ports on the Intel Crown Bay board, 2 of which are connected to Topcliff usb host 0 and the other 2 connected to usb host 1. USB devices inserted in the ports connected to usb host 1 cannot get detected due to wrong IRQ assigned to the controller. Actually we need apply the PCI interrupt pin swizzling logic to all devices on the Topcliff chipset when configuring the PIRQ routing. This was observed on usb ports, but device 6 and 10 irqs are also wrong. Correct them all together. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: crownbay: Enable DM RTC supportBin Meng2015-07-14-0/+8
| | | | | | | | | | | | | | | | | | | | | Add a RTC node in the device tree to enable DM RTC support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * cmd: date: Change to use CONFIG_DM_RTC instead of CONFIG_DM_I2CBin Meng2015-07-14-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Currently CONFIG_DM_I2C is used in cmd_date.c for driver model, but it should be actually CONFIG_DM_RTC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * dm: rtc: Support mc146818 driver in driver modelBin Meng2015-07-14-108/+204
| | | | | | | | | | | | | | | | | | | | | | | | Add driver model support to the mc146818 rtc driver. Also clean up the driver a little bit for coding convention issues. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: crownbay: Add MP initializationBin Meng2015-07-14-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Crown Bay board has a TunnelCreek processor which supports hyper-threading. Add /cpus node in the crownbay.dts and enable the MP initialization. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (modified to remove error: overriding the value of OF_CONTROL. Old value: "y", new value: "y")
| | * x86: Clean up lapic codesBin Meng2015-07-14-183/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit cleans up the lapic codes: - Delete arch/x86/include/asm/lapic_def.h, and move register and bit defines into arch/x86/include/asm/lapic.h - Use MSR defines from msr-index.h in enable_lapic() and disable_lapic() - Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and CONFIG_AP_IN_SIPI_WAIT - Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as it is not apic related and only used by ivybridge - Fix coding convention issues Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Move lapic_setup() call into init_bsp()Bin Meng2015-07-14-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently lapic_setup() is called before calling mp_init(), which then calls init_bsp() where it calls enable_lapic(), which was already enabled in lapic_setup(). Hence move lapic_setup() call into init_bsp() to avoid the duplication. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Move MP initialization codes into a common placeBin Meng2015-07-14-73/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is common to all x86 processors, except detect_num_cpus() which varies from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the new 'get_count' method for baytrail and cpu_x86 drivers. Now we call cpu_get_count() in mp_init() to get the number of CPUs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONSBin Meng2015-07-14-1/+0
| | | | | | | | | | | | | | | | | | | | | Ivybridge is not ready for U-Boot MP initialization yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * dm: cpu: Add a new get_count method to cpu uclassBin Meng2015-07-14-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | Introduce a new method 'get_count' in the UCLASS_CPU ops to get the number of CPUs in the system. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: kconfig: Fix minor nits in MAX_CPUSBin Meng2015-07-14-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move MAX_CPUS definition after SMP so that it shows below SMP in the menuconfig. Also replace the leading spaces in the MAX_CPUS section with tabs to conform coding standard. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMPBin Meng2015-07-14-0/+2
| | | | | | | | | | | | | | | | | | | | | MAX_CPUS and AP_STACK_SIZE are only meaningful when SMP is on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: dm: Clean up cpu driversBin Meng2015-07-14-55/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit does the following to clean up x86 cpu dm drivers: - Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated file arch/x86/cpu/cpu_x86.c - Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent naming with other dm drivers - Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly the same as the one in the intel baytrail cpu driver - Update intel baytrail cpu driver to use cpu_x86_get_desc() and cpu_x86_bind() Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * dm: cpu: Test against cpu_ops->get_info in cpu_get_info()Bin Meng2015-07-14-1/+1
| | | | | | | | | | | | | | | | | | | | | In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see if it is NULL. It should test against cpu_ops->get_info. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| | * dm: cpu: Fix undefined ENOSYS build errorBin Meng2015-07-14-0/+2
| | | | | | | | | | | | | | | | | | | | | Include <errno.h> otherwise ENOSYS is undefined. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * dm: spi: Correct minor nits in ICH driverSimon Glass2015-07-14-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Tidy up three minor problems in this file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| | * spi: sf: Print the error code on failureSimon Glass2015-07-14-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than just 'ERROR', display the error code, which may be useful, at least with driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
| | * x86: fsp: Move FspInitEntry call to board_init_f()Bin Meng2015-07-14-22/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far. It worked pretty well but looks not that good. Apart from doing too much work than just enabling CAR, it cannot read the configuration data from device tree at that time. Now we want to move it a little bit later as part of init_sequence_f[] being called by board_init_f(). This way it looks and works better in the U-Boot initialization path. Due to FSP's design, after calling FspInitEntry it will not return to its caller, instead it jumps to a continuation function which is given by bootloader with a new stack in system memory. The original stack in the CAR is gone, but its content is perserved by FSP and described by a bootloader temporary memory HOB. Technically we can recover anything we had before in the previous stack, but that is way too complicated. To make life much easier, in the FSP continuation routine we just simply call fsp_init_done() and jump back to car_init_ret() to redo the whole board_init_f() initialization, but this time with a non-zero HOB list pointer saved in U-Boot's global data so that we can bypass the FspInitEntry for the second time. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Tested-by: Simon Glass <sjg@chromium.org>
| | * x86: fsp: Load GDT before calling FspInitEntryBin Meng2015-07-14-2/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the FSP execution environment GDT is setup by U-Boot in arch/x86/cpu/start16.S, which works pretty well. But if we try to move the FspInitEntry call a little bit later to better fit into U-Boot's initialization sequence, FSP will fail to bring up the AP due to #GP fault as AP's GDT is duplicated from BSP whose GDT is now moved into CAR, and unfortunately FSP calls AP initialization after it disables the CAR. So basically the BSP's GDT still refers to the one in the CAR, whose content is no longer available, so when AP starts up and loads its segment register, it blows up. To resolve this, we load GDT before calling into FspInitEntry. The GDT is the same one used in arch/x86/cpu/start16.S, which is in the ROM and exists forever. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Add Kconfig options to be used by arch/x86/cpu/config.mkBin Meng2015-07-14-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add RESET_SEG_START, RESET_SEG_SIZE and RESET_VEC_LOC Kconfig options and make arch/x86/cpu/config.mk use these options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Tested-by: Simon Glass <sjg@chromium.org>
| | * builderthread.py: Keep 'SPL'Tom Rini2015-07-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | On i.MX platforms the SPL binary is called "SPL" so make sure we keep that. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-07-14-41/+151
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| | * spi: cadence_qspi: add device tree binding docVikas Manocha2015-07-03-5/+28
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the device tree binding doc for the cadence qspi controller & also removes the not needed properties from the stv0991 device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * spi: cadence_qspi: support FIFO width other than 4 bytesVikas Manocha2015-07-03-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes the code compatible with FIFO depths other than 4 bytes. It also simplify read/write FIFO loops. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * spi: cadence_qspi: get sram size from device treeVikas Manocha2015-07-03-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * spi: cadence_qspi: move the sram partition in initVikas Manocha2015-07-03-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to re-configure sram partition for every read/write for better full use of sram for read or write. This patch divides the half sram for read & half for write once at initialization. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * stv0991: configure device tree for cadence qspi & flashVikas Manocha2015-07-03-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | This patch add the device tree entry for qspi controller & spi flash memory. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * stv0991: enable cadence qspi controller & spi flashVikas Manocha2015-07-03-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | This patch does all the board configurations required to use the qspi controller & attached spi flash memory. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * stv0991: configure clock & pad muxing for qspiVikas Manocha2015-07-03-1/+42
| | | | | | | | | | | | | | | | | | | | | | | | stv0991 has cadence qspi controller for flash interfacing, this patch configures the device pads & clock for the controller. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * stv0991: remove define CONFIG_OF_SEPARATE from board fileVikas Manocha2015-07-03-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_OF_SEPARATE is default define with CONFIG_OF_CONTROL, removing this define from the board file to avoid multiple definition warning. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * stv0991: move OF_CONTROL config to defconfigVikas Manocha2015-07-03-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * stv0991: enable saving enrironment in spi flashVikas Manocha2015-07-03-2/+3
| | | | | | | | | | | | | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| * | RFC: Deprecate MAKEALLSimon Glass2015-07-14-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since buildman now includes most of the features of MAKEALL it is probably time to talk about deprecating MAKEALL. Comments welcome. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | Prepare v2015.07Tom Rini2015-07-14-1/+1
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
| * | scsi: fix compiler warning with DEBUG and 48bit LBAsAndre Przywara2015-07-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2b42c9317db ("ahci: support LBA48 data reads for 2+TB drives") introduced conditional code which triggers a warning when compiled with DEBUG enabled: In file included from common/cmd_scsi.c:12:0: common/cmd_scsi.c: In function 'scsi_read': include/common.h:109:4: warning: 'smallblks' may be used uninitialized in this function [-Wmaybe-uninitialized] ... Since this is for debug only, take the easy way and initialize the variable explicitly on declaration to avoid the warning. (Fix a nearby whitespace error on the way.) Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Andre Przywara <osp@andrep.de>
generated by cgit v1.1 at 2024-11-09 19:26:27 +0000