summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* armv8: Move secure_ram variable out of generic global dataYork Sun2016-07-15-63/+69
| | | | | | | Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com>
* Revert "armv8: Enable CPUECTLR.SMPEN for coherency"Tom Rini2016-07-14-8/+0
| | | | | | | | | Upon further review this breaks most other platforms as we need to check what core we're running on before touching it at all. This reverts commit d73718f3236c520a92efa401084c658e6cc067f3. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-07-12-23/+773
|\
| * x86: link: Correct a failure in DRAM initSimon Glass2016-07-12-0/+5
| | | | | | | | | | | | | | | | | | | | With the change to set up pinctrl after relocation, link fails to boot. Add a special case in the link code to handle this. Fixes: d8906c1f (x86: Probe pinctrl driver in cpu_init_r()) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add Advantech SOM-DB5800/SOM-6867 supportGeorge McCollister2016-07-12-1/+524
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Advantech SOM-DB5800 with the SOM-6867 installed. This is very similar to conga-qeval20-qa3-e3845 in that there is a reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867) installed. Currently supported: - 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on SOM-DB5800. - 4x USB 2.0 (EHCI) - Video - SATA - Ethernet - PCIe - Realtek ALC892 HD Audio Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO HDA_SDI0 is set in DT to enable HD Audio codec. Pin defaults for codec pin complexs are not changed. Not supported: - Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500) - USB 3.0 (XHCI) - TPM Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: baytrail: acpi: Hide internal UART per GNVS settingBin Meng2016-07-12-11/+8
| | | | | | | | | | | | | | | | | | | | If global NVS says internal UART is not enabled, hide it in the ASL code so that OS won't see it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: acpi: Pack global NVS into ACPI tableBin Meng2016-07-12-2/+32
| | | | | | | | | | | | | | | | | | | | Now that platform-specific ACPI global NVS is added, pack it into ACPI table and get its address fixed up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Introduce ACPI global NVSBin Meng2016-07-12-0/+41
| | | | | | | | | | | | | | | | This introduces quark-specific ACPI global NVS structure, defined in both C header file and ASL file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Introduce ACPI global NVSBin Meng2016-07-12-0/+81
| | | | | | | | | | | | | | | | | | | | This introduces baytrail-specific ACPI global NVS structure, defined in both C header file and ASL file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: conga-qeval20-qa3: Add support for internal UARTStefan Roese2016-07-12-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to enable and use the internal BayTrail UART instead of the one integrated in the Super IO Winbond chip. For this, a 2nd defconfig file is added. This is useful for tests done for the congatec SoM used on baseboards without such a Super IO chip. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Wrap setup_internal_uart() call with CONFIG_INTERNAL_UARTBin Meng2016-07-12-1/+1
| | | | | | | | | | | | | | | | | | | | For any FSP-enabled boards that want to enable debug UART support, setup_internal_uart() will be called, but this API is only available on BayTrail platform. Change to wrap it with CONFIG_INTERNAL_UART. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Introduce a Kconfig option for the internal UARTBin Meng2016-07-12-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | There are quite a number of BayTrail boards that uses an external SuperIO chipset to provide the legacy UART. For such cases, it's better to have a Kconfig option to enable the internal UART. So far BayleyBay and MinnowMax boards are using internal UART as the U-Boot console, enable this on these two boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * pci: Add board_ prefix to should_load_oprom() and make it weakBin Meng2016-07-12-2/+2
| | | | | | | | | | | | | | | | | | For consistency with board_should_run_oprom(), do the same to should_load_oprom(). Board support codes can provide this one to override the default weak one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * pci: Make load_oprom and run_oprom independentBin Meng2016-07-12-4/+1
| | | | | | | | | | | | | | | | | | At present should_load_oprom() calls board_should_run_oprom() to determine whether oprom should be loaded. But sometimes we just want to load oprom without running. Make them independent. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * pci: Remove CONFIG_ALWAYS_LOAD_OPROMBin Meng2016-07-12-2/+0
| | | | | | | | | | | | | | This option is defined at nowhere. Remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2016-07-11-117/+450
|\ \
| * | dm: spi: Read default speed and mode values from DTVignesh R2016-07-09-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of DT boot, don't read default speed and mode for SPI from CONFIG_*, instead read from DT node. This will make sure that boards with multiple SPI/QSPI controllers can be probed at different bus frequencies and SPI modes. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHzVignesh R2016-07-09-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better throughput. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | defconfig: k2g_evm_defconfig: Enable Cadence QSPI controllerVignesh R2016-07-09-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable Cadence QSPI controller support to use QSPI on K2G SoC. Also enable Spansion flash support to access s25fl512s flash present on K2G QSPI bus. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: K2G: Add support for QSPI controllerVignesh R2016-07-09-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | K2G SoC has a Cadence QSPI controller to communicate with NOR flash devices. Add DT nodes to support the same. Also, K2G EVM has a s25fl512s flash connect to QSPI bus at CS 0. Add nor flash slave node for the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | spi: cadence_quadspi: Enable QUAD mode based on DT dataVignesh R2016-07-09-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | spi: cadence_qspi_apb: Support 32 bit AHB addressVignesh R2016-07-09-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AHB address can be as long as 32 bit, hence remove the CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT and read as u32 value, it anyway does not make sense to mask upper bits. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | defconfig: k2g_evm_defconfig: enable SPI driver modelVignesh R2016-07-09-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPI and SPI Flash driver model as K2G SPI controller driver supports driver model. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: k2g: add support for Davinci SPI controllerVignesh R2016-07-09-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | K2G SoC has 4 SPI instances that are compatible with davinci_spi controller(present on previous generation of Keystone2 devices). Add DT nodes for the same. K2G EVM has a N25Q128A13 SPI NOR flash connected on SPI-1. Add DT bindings for the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | defconfig: k2l_evm_defconfig: enable SPI driver modelVignesh R2016-07-09-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPI and SPI Flash driver model as K2L SPI controller driver supports driver model. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: k2l: Enable Davinci SPI controllerVignesh R2016-07-09-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that davinci_spi driver has been converted to DM framework, enable the same in DT. Also add "spi-flash" as compatible property to n25q128a11 node as it is required for flash device to be probed in U-Boot. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | defconfig: k2e_evm_defconfig: enable SPI driver modelVignesh R2016-07-09-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPI and SPI Flash driver model as K2E SPI controller driver supports driver model. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: k2e: Enable Davinci SPI controllerVignesh R2016-07-09-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that davinci_spi driver has been converted to DM framework, enable the same in DT. Also add "spi-flash" as compatible property to n25q128a11 node as it is required for flash device to be probed in U-Boot. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | defconfig: k2hk_evm_defconfig: enable SPI driver modelVignesh R2016-07-09-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPI and SPI Flash driver model as K2HK SPI controller driver supports driver model. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: k2hk: Enable Davinci SPI controllerVignesh R2016-07-09-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that davinci_spi driver has been converted to DM framework, enable the same in DT. Also add "spi-flash" as compatible property to n25q128a11 node as it is required for flash device to be probed in U-Boot. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: keystone2: add SPI aliases for davinci SPI nodesVignesh R2016-07-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add aliases for SPI nodes in order for it to be probed by the DM framework. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | keystone2: spi: do not define DM_SPI and DM_SPI_FLASH for SPL buildVignesh R2016-07-09-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since Keystone2 devices do not have support DM in SPL, do not define DM_SPI and DM_SPI_FLASH for SPL build. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | spi: davinci_spi: Convert to driver to adapt to DMVignesh R2016-07-09-89/+240
| | | | | | | | | | | | | | | | | | | | | | | | Convert davinci_spi driver so that it complies with SPI DM framework. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | dm: core: implement dev_map_physmem()Vignesh R2016-07-09-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This API helps to map physical register addresss pace of device to virtual address space easily. Its just a wrapper around map_physmem() with MAP_NOCACHE flag. Signed-off-by: Vignesh R <vigneshr@ti.com> Suggested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * | spi: spi-uclass: fix typo in debug outputAnatolij Gustschin2016-07-06-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | | tools: patman: Handle missing 'END' in non-last commit of a seriesBin Meng2016-07-11-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following python error: Traceback (most recent call last): File "./tools/patman/patman", line 144, in <module> series = patchstream.FixPatches(series, args) File "./tools/patman/patchstream.py", line 477, in FixPatches commit = series.commits[count] IndexError: list index out of range is seen when: - 'END' is missing in those tags - those tags are put in the last part in a commit message - the commit is not the last commit of the series Add testing logic to see if a new commit starts. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | tools: patman: Handle missing blank line for 'Series-changes'Bin Meng2016-07-11-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | 'Series-changes' uses blank line to indicate its end. If that is missing, series internal state variable 'in_change' may be wrong. Correct its state. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | tools: patman: Generate cover letter correctly when 'END' is missingBin Meng2016-07-11-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If 'END' is missing in a 'Cover-letter' section, and that section happens to show up at the very end of the commit message, and the commit is the last commit of the series, patman fails to generate cover letter for us. Handle this in CloseCommit of patchstream. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | tools: patman: Handle tag sections without an 'END'Bin Meng2016-07-11-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'Cover-letter', 'Series-notes' and 'Commit-notes' tags require an 'END' to be put at the end of its section. If we forget to put an 'END' in those sections, and these sections are followed by another patman tag, patman generates incorrect patches. This adds codes to handle such scenario. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | tools: patman: Use cover_match for 'Cover-letter'Bin Meng2016-07-11-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Like other patman tags, use a new variable cover_match to indicate a match for 'Cover-letter'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | dm: Sort the uclass id in alphabetical orderBin Meng2016-07-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Some uclass ids are out of order. Per the comments, sort them in alphabetical order. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | sandbox: Find keyboard driver using driver modelSimon Glass2016-07-11-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | The cros-ec keyboard is always a child of the cros-ec node. Rather than searching the device tree, looking at the children. Remove the compat string which is now unused. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | fdt: x86: Tidy up a few COMPAT string definitionsSimon Glass2016-07-11-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | The 'COMPAT_' part should appear only once so drop the duplicate part. It is ignored anyway, but let's keep things consistent. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | fdt: Add a note to avoid adding new compatible stringsSimon Glass2016-07-11-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | The list is shrinking and we should avoid adding new things. Instead, a proper driver should be created with driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | fdt: Drop unused exynos compatible stringsSimon Glass2016-07-11-4/+0
| | | | | | | | | | | | | | | | | | | | | A few drivers have moved to driver model, so we can drop these strings. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | x86: fdt: Drop the unused compatible strings in fdtdecSimon Glass2016-07-11-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | We have drivers for several more devices now, so drop the strings which are no-longer used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | common: block: fix compiler error with CONFIG_FASTBOOT_FLASH_MMC_DEVXu Ziyuan2016-07-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following compiler error: common/fb_mmc.c: In function ‘fb_mmc_erase’: common/fb_mmc.c:209:17: error: ‘struct blk_desc’ has no member named ‘block_erase’ Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | dm: gpio: MPC85XX GPIO platform data supportHamish Martin2016-07-11-7/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a platform data structure for the MPC85XX GPIO driver to allow use of the driver without device tree. Users should define the GPIO blocks for their platform like this: struct mpc85xx_gpio_plat gpio_blocks[] = { { .addr = 0x130000, .ngpios = 32, }, { .addr = 0x131000, .ngpios = 32, }, }; U_BOOT_DEVICES(my_platform_gpios) = { { "gpio_mpc85xx", &gpio_blocks[0] }, { "gpio_mpc85xx", &gpio_blocks[1] }, }; This is intended to build upon the recent submission of the base MPC85XX driver from Mario Six. We need to use that new driver without dts support and this patch gives us that flexibility. This has been tested on a Freescale T2080 CPU, although only the first GPIO block. Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Reviewed-by: Mario Six <mario.six@gdsys.cc> Tested-by: Mario Six <mario.six@gdsys.cc> Acked-by: Simon Glass <sjg@chromium.org>
* | | dm: dfu: mmc: Support CONFIG_BLK in DFU for MMCSimon Glass2016-07-11-6/+5
| | | | | | | | | | | | | | | | | | | | | Update the method of accessing the block device so that it works with CONFIG_BLK enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | dm: spl: mmc: Support CONFIG_BLK in SPL MMCSimon Glass2016-07-11-3/+3
| | | | | | | | | | | | | | | | | | | | | Update the method of accessing the block device so that it works with CONFIG_BLK enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-07 09:10:13 +0000