summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* imx: mx6ul: skip setting ahb ratePeng Fan2016-03-25-7/+12
| | | | | | | | To i.MX6UL, default ARM rate and AHB rate is 396M and 198M, no need to set them. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6: Fix incorrect clear mmdc_ch0 handshake maskYe Li2016-03-25-1/+4
| | | | | | | | | | | Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* Merge branch 'next'Stefano Babic2016-03-20-4/+1127
|\
| * mx7: Distinguish between dual and solo versionsFabio Estevam2016-03-09-0/+21
| | | | | | | | | | | | | | | | | | | | Read the number of cores in the fuses to distinguish between the dual and solo versions. Tested on a mx7d sabresd and on a mx7solo warp7. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * mx7dsabresd: Define serial port locallyFabio Estevam2016-03-09-1/+2
| | | | | | | | | | | | | | | | | | CONFIG_MXC_UART_BASE should not be defined in mx7_common.h as the console port can vary from board to board. Define CONFIG_MXC_UART_BASE locally instead. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx7_common: Remove unexisting optionsFabio Estevam2016-03-09-3/+0
| | | | | | | | | | | | | | CONFIG_IMX_FIXED_IVT_OFFSET and CONFIG_FSL_CLK are not used anywhere, so just remove them. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * arm: imx: Add support for GE Bx50v3 boardsAkshay Bhat2016-03-09-0/+1104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for GE B450v3, B650v3 and B850v3 boards. The boards are based on Advantech BA16 module which has a i.MX6D processor. The boards support: - FEC Ethernet - USB Ports - SDHC and MMC boot - SPI NOR - LVDS and HDMI display Basic information about the module: - Module manufacturer: Advantech - CPU: Freescale ARM Cortex-A9 i.MX6D - SPECS: Up to 2GB Onboard DDR3 Memory; Up to 16GB Onboard eMMC NAND Flash Supports OpenGL ES 2.0 and OpenVG 1.1 HDMI, 24-bit LVDS 1x UART, 2x I2C, 8x GPIO, 4x Host USB 2.0 port, 1x USB OTG port, 1x micro SD (SDHC),1x SDIO, 1x SATA II, 1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2 Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* | dm: blk: Add tests for block devicesSimon Glass2016-03-17-0/+97
| | | | | | | | | | | | | | Add some tests to check that block devices work as expected. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* | dm: sandbox: Drop the pre-DM host implementationSimon Glass2016-03-17-90/+0
| | | | | | | | | | | | | | | | Driver model is used for host device block devices now, so we don't need the old code. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* | dm: sandbox: Switch over to use DM for block devicesSimon Glass2016-03-17-0/+1
| | | | | | | | | | | | | | | | Now that the drivers used by sandbox support CONFIG_BLK, we can switch sandbox over to use driver model for block devices. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* | dm: usb: Unbind old block devices when shutting down USBSimon Glass2016-03-17-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When 'usb start' is used, block devices are created for any USB flash sticks and disks, etc. When 'usb stop' is used, these block devices are currently not removed. We don't want old block devices hanging around since they can still be visible to U-Boot. Therefore, when USB is shut down, remove and unbind all the block devices created by the USB subsystem. Possibly we should unbind all devices which don't cause problems by being unbound. Most likely we can remove everything except USB controllers, hubs and emulators. We can consider that later. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* | buildman: Clarify the use of -VSimon Glass2016-03-17-2/+3
| | | | | | | | | | | | | | | | | | This option outputs to the log file, not to the terminal. Clarify that in the help, and add a mention of it in the README. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | buildman: Add a way to specific a full toolchain prefixSimon Glass2016-03-17-110/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present buildman allows you to specify the directory containing the toolchain, but not the actual toolchain prefix. If there are multiple toolchains in a single directory, this can be inconvenient. Add a new 'toolchain-prefix' setting to the settings file, which allows the full prefix (or path to the C compiler) to be specified. Update the documentation to match. Suggested-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* | buildman: Allow branch names which conflict with directoriesSimon Glass2016-03-17-0/+7
| | | | | | | | | | | | | | | | | | | | At present if you try to use buildman with the branch 'test' it will complain that it is unsure whether you mean the branch or the directory. This is a feature of the 'git log' command that buildman uses. Fix it by resolving the ambiguity. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | dm: ns16550: Add support for reg-offset propertyMichal Simek2016-03-17-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Moved the new field to the end of the struct to avoid problems: Signed-off-by: Simon Glass <sjg@chromium.org>
* | Revert "fdt: fix address cell count checking in fdt_translate_address()"Przemyslaw Marczak2016-03-17-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 71105f50fedddfa5b0535d102c3d5078671721ad. The reverted commit was applied for a temporary to unbreak few Exynos boards on the release. After the discussion about the change, this commit should be avoided. Fixed device-tree for Exynos, allows reverting it without any issues. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | dts:exynos:update pinctrl size-cells and fix child regsPrzemyslaw Marczak2016-03-17-29/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is required to avoid warnings about invalid size-cells defined in device-tree pinctrl nodes for Exynos. Tested on: - Odroid U3 - Odroid XU3 Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* | gpio: Report errors when GPIOs cannot be readSimon Glass2016-03-17-7/+27
| | | | | | | | | | | | | | Some controllers do not allow the output value to be read. Detect this and report the error in that case. Signed-off-by: Simon Glass <sjg@chromium.org>
* | cmd_dhry.c: Use lldiv for vax_mips calculation as wellTom Rini2016-03-17-1/+1
| | | | | | | | | | | | | | | | | | | | Since dhry_per_sec is a u64 we must also use lldiv here when working with it. Otherwise: ../lib/dhry/cmd_dhry.c:(.text.do_dhry+0xd8): undefined reference to `__udivdi3' On some platforms. Signed-off-by: Tom Rini <trini@konsulko.com>
* | x86: Add congatec conga-QA3/E3845-4G (Bay Trail) supportStefan Roese2016-03-17-0/+506
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM, installed on the congatec Qseven 2.0 evaluation carrier board (conga-QEVAL). Its port is very similar to the MinnowboardMAX port and also uses the Intel FSP as described in doc/README.x86. Currently supported are the following interfaces / devices: - UART (via Winbond legacy SuperIO chip on carrier board) - Ethernet (PCIe Intel I210 / E1000) - SPI including SPI NOR as boot-device - USB 2.0 - SATA via U-Boot SCSI IF - eMMC - Video (HDMI output @ 800x600) - PCIe Not supported yet is: - I2C - USB 3.0 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Add support for the samus chromebookSimon Glass2016-03-17-1/+876
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Support a chained-boot development flowSimon Glass2016-03-17-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI without any 16-bit init. This can help during development by allowing U-Boot to avoid doing all the init required by the platform. U-Boot expects its GDT to be set up correctly by its 16-bit code. If coreboot doesn't do this (because it hasn't run the payload setup code yet) then this won't happen. In this case we cannot rely on the GDT settings. U-Boot will hang or crash if these are wrong. Provide a development-only option to set up the GDT correctly. This is just a hack so you can jump to U-Boot from any stage of coreboot, not just at the end. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: dts: Drop memory SPD compatible stringSimon Glass2016-03-17-3/+0
| | | | | | | | | | | | | | | | This is not needed now that the memory controller driver has the SPD data in its own node. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Convert to use the common SDRAM codeSimon Glass2016-03-17-311/+83
| | | | | | | | | | | | | | Adjust the existing implementation to use the new common SDRAM init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Add common SDRAM-init codeSimon Glass2016-03-17-0/+327
| | | | | | | | | | | | | | | | | | The code to call the memory reference code is common to several Intel CPUs. Add common code for performing this init. Intel calls this 'Pre-EFI-Init' (PEI), where EFI stands for Extensible Firmware Interface. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Move common PCH code into a common placeSimon Glass2016-03-17-84/+99
| | | | | | | | | | | | | | | | The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dhry: Correct dhrystone calculation for fast machinesSimon Glass2016-03-17-3/+5
| | | | | | | | | | | | | | At present samus reports about 5600 DMIPS. With the default iteration count this is OK, but if 10 million runs are performed it overflows. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Add a 64-bit division routine to the private librarySimon Glass2016-03-17-1/+247
| | | | | | | | | | | | | | | | | | | | | | | | This is missing, with causes lldiv() to fail on boards with use the private libgcc. Add the missing routine. Code is available for using the CLZ instruction but it is not enabled at present. This comes from coreboot version 4.0. Signed-off-by: Simon Glass <sjg@chromium.org>
* | x86: Fix a header nit in x86-chromebook.hSimon Glass2016-03-17-1/+0
| | | | | | | | | | | | | | There is an extra line in the comment in the header. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Add a function to set the IOAPIC IDSimon Glass2016-03-17-0/+18
| | | | | | | | | | | | | | Add a function to set the ID in the IOAPIC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Update README for new developmentsSimon Glass2016-03-17-3/+13
| | | | | | | | | | | | | | Update a few points which have become out-of-date. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Use white on black for the console on chromebooksSimon Glass2016-03-17-0/+2
| | | | | | | | | | | | | | | | This is a little easier on the eyes, particularly when the backlight is set to maximum. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Add a default address for reference codeSimon Glass2016-03-17-0/+2
| | | | | | | | | | | | | | | | Add an address which can be used for loading and running the reference code when needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: broadwell: Add video supportSimon Glass2016-03-17-1/+1174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a video driver for Intel's broadwell integrated graphics controller. This uses a binary blob for most init, with the driver just performing a few basic tasks. This driver supports VESA as the mode-setting mechanism. Since most boards don't support driver model yet with VESA, a special case is added to the Kconfig for broadwell. Eventually all boards will use driver model and this can be removed. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: broadwell: Add support for high-speed I/O lane with MESimon Glass2016-03-17-0/+58
| | | | | | | | | | | | | | | | Provide a way to determine the HSIO (high-speed I/O) version supported by the Intel Management Engine (ME) implementation on the platform. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: broadwell: Add a GPIO driverSimon Glass2016-03-17-0/+208
| | | | | | | | | | | | | | Add a GPIO driver for the GPIO peripheral found on broadwell devices. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: broadwell: Add support for SDRAM setupSimon Glass2016-03-17-0/+509
| | | | | | | | | | | | | | | | | | Broadwell uses a binary blob called the memory reference code (MRC) to start up its SDRAM. This is similar to ivybridge so we can mostly use common code for running this blob. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: broadwell: Add power-control supportSimon Glass2016-03-17-0/+220
| | | | | | | | | | | | | | | | | | | | Broadwell requires quite a bit of power-management setup. Add code to set this up correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598373/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: broadwell: Add reference code supportSimon Glass2016-03-17-0/+114
| | | | | | | | | | | | | | | | Broadwell needs a special binary blob to set up the PCH. Add code to run this on start-up. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: broadwell: Add an LPC driverSimon Glass2016-03-17-0/+110
| | | | | | | | | | | | | | | | Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly uses common code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: broadwell: Add a northbridge driverSimon Glass2016-03-17-0/+60
| | | | | | | | | | | | | | | | Add a driver for the broadwell northbridge. This sets up the location of several blocks of registers. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: broadwell: Add a SATA driverSimon Glass2016-03-17-0/+270
| | | | | | | | | | | | | | | | Add a SATA driver for broadwell. This supports connecting an SSD and the usual U-Boot commands to read and write data. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: broadwell: Add a pinctrl driverSimon Glass2016-03-17-0/+590
| | | | | | | | | | | | | | | | | | | | | | GPIO pins need to be set up on start-up. Add a driver to provide this, configured from the device tree. The binding is slightly different from the existing ICH6 binding, since that is quite verbose. The new binding should be just as extensible. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: broadwell: Add a PCH driverSimon Glass2016-03-17-0/+839
| | | | | | | | | | | | | | Add a driver for the broadwell low-power platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Add basic support for broadwellSimon Glass2016-03-17-0/+1246
| | | | | | | | | | | | | | | | This adds the broadwell architecture, with the CPU driver and some useful header files. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: dts: Update the pinctrl binding a littleSimon Glass2016-03-17-10/+11
| | | | | | | | | | | | | | Make a few minor updates to make the meaning clearer. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Add support for running Intel reference codeSimon Glass2016-03-17-1/+36
| | | | | | | | | | | | | | | | | | | | | | | | Intel has invented yet another binary blob which firmware is required to run. This is run after SDRAM is ready. It is linked to load at a particular address, typically 0, but is a relocatable ELF so can be moved if required. Add support for this in the build system. The file should be placed in the board directory, and called refcode.elf. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Drop all the old pin configuration codeSimon Glass2016-03-17-334/+0
| | | | | | | | | | | | | | | | We don't need this anymore - we can use device tree and the new pinconfig driver instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: gpio: Allow the pinctrl driver to set up the pin configSimon Glass2016-03-17-175/+15
| | | | | | | | | | | | | | | | Rather than setting up the pin configuration in the GPIO driver, use the new pinctrl driver to do it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Add an ICH6 pin configuration driverSimon Glass2016-03-17-0/+219
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver which sets up the pin configuration on x86 devices with an ICH6 (or later) Platform Controller Hub. The driver is not in the pinctrl uclass due to some oddities of the way x86 devices work: - The GPIO controller is not present in I/O space until it is set up - This is done by writing a register in the PCH - The PCH has a driver which itself uses PCI, another driver - The pinctrl uclass requires that a pinctrl device be available before any other device can be probed It would be possible to work around the limitations by: - Hard-coding the GPIO address rather than reading it from the PCH - Using special x86 PCI access to set the GPIO address in the PCH However it is not clear that this is better, since the pin configuration driver does not actually provide normal pin configuration services - it simply sets up all the pins statically when probed. While this remains the case, it seems better to use a syscon uclass instead. This can be probed whenever it is needed, without any limitations. Also add an 'invert' property to support inverting the input. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-14 22:38:20 +0000