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* | x86: ivybridge: Convert report_platform to DM PCI APISimon Glass2016-01-24-7/+8
| | | | | | | | | | | | | | Convert these functions to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Convert SDRAM init to use driver modelSimon Glass2016-01-24-38/+101
| | | | | | | | | | | | | | | | | | SDRAM init needs access to the Northbridge controller and the Intel Management Engine device. Add the latter to the device tree and convert all of this code to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: chromebook_link: Enable the syscon uclassSimon Glass2016-01-24-0/+2
| | | | | | | | | | | | | | | | We will use a system controller to model the Intel Management Engine. Enable this for link. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Convert sdram_initialise() to use DM PCI APISimon Glass2016-01-24-9/+10
| | | | | | | | | | | | | | | | Convert this function to use the the driver model PCI API. We just need to pass in the northbridge device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Convert dram_init() to use DM PCI APISimon Glass2016-01-24-14/+25
| | | | | | | | | | | | | | | | Convert the top part of the DRAM init to use the driver model PCI API. Further work will complete the transformation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Convert enable_usb_bar() to use DM PCI APISimon Glass2016-01-24-17/+17
| | | | | | | | | | | | | | | | | | Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Use the I2C driver to perform SMbus initSimon Glass2016-01-24-36/+35
| | | | | | | | | | | | | | | | Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: i2c: Add a stub driver for Intel I2C/SMbusSimon Glass2016-01-24-0/+61
| | | | | | | | | | | | | | | | | | | | | | This is used on most Intel platforms. We don't have a driver for it yet, but add a stub to handle the init. For now this targets ivybridge so we may want to add a device tree binding and generalise it when other platforms are supported. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Enable DM_USB for link and pantherSimon Glass2016-01-24-0/+4
| | | | | | | | | | | | | | Move these two boards to use driver model for USB. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Convert lpc init code to DM PCI APISimon Glass2016-01-24-63/+66
| | | | | | | | | | | | | | | | Adjust this code to use the driver model PCI API. This is all called through lpc_init_extra(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Drop the special PCI driverSimon Glass2016-01-24-48/+1
| | | | | | | | | | | | | | | | There is nothing special about the ivybridge pci driver now, so just use the generic one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move LPC init into the LPC probe() methodSimon Glass2016-01-24-14/+9
| | | | | | | | | | | | | | | | Drop the lpc_init_extra() function and just use the post-relocation LPC probe() instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move lpc_enable() into gma.cSimon Glass2016-01-24-9/+4
| | | | | | | | | | | | | | | | This graphics init code is best placed in the gma init code. Move the code and drop the function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Use driver model PCI API in sata.cSimon Glass2016-01-24-49/+45
| | | | | | | | | | | | | | Adjust the functions in this file to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Use the SATA driver to do the initSimon Glass2016-01-24-10/+8
| | | | | | | | | | | | | | | | Instead of manually initing the device, probe the SATA device and move the init there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Drop the unused bd82x6x_init_extra()Simon Glass2016-01-24-18/+0
| | | | | | | | | | | | | | This function does nothing now so can be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Do the SATA init before relocationSimon Glass2016-01-24-11/+36
| | | | | | | | | | | | | | | | | | The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | ahci: Add a disk-controller uclassSimon Glass2016-01-24-0/+25
| | | | | | | | | | | | | | | | | | Add a uclass ID for a disk controller. This can be used by AHCI/SATA or other controller types. There are no operations and no interface so far, but it is possible to probe a SATA device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Drop unnecessary northbridge setupSimon Glass2016-01-24-20/+0
| | | | | | | | | | | | | | This is done by default with PCI auto-config. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Use driver model PCI API in bd82x6x.cSimon Glass2016-01-24-16/+7
| | | | | | | | | | | | | | | | | | Adjust most of the remaining functions in this file to use the driver model PCI API. The one remaining function is bridge_silicon_revision() which will need a little more work. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move northbridge and PCH init into driversSimon Glass2016-01-24-55/+12
| | | | | | | | | | | | | | | | | | | | Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Bring up northbridge, pch and lpc after the CPUsSimon Glass2016-01-24-2/+18
| | | | | | | | | | | | | | | | | | | | These devices currently need to be inited early in boot. Once we have the init in the right places (with each device doing its own init and no problems with ordering) we should be able to remove this. For now it is needed to keep things working. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Don't show an error when the MRC cache is up to dateSimon Glass2016-01-24-1/+5
| | | | | | | | | | | | | | | | | | | | When the final MRC cache record is the same as the one we want to write, we skip writing since there is no point. This is normal behaviour. Avoiding printing an error when this happens. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Make x86_init_cpus() staticSimon Glass2016-01-24-3/+1
| | | | | | | | | | | | | | | | There are no other implementations of this function, and boards that need it can implement a CPU driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move early init code into northbridge.cSimon Glass2016-01-24-82/+67
| | | | | | | | | | | | | | | | This code is now part of the northbridge driver, so move it into the same place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Drop the dead MTRR codeSimon Glass2016-01-24-10/+0
| | | | | | | | | | | | | | This is not used and MTRRs are set up elsewhere now. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Set up the thermal target correctlySimon Glass2016-01-24-11/+10
| | | | | | | | | | | | | | | | | | This uses a non-existent node at present. It should use the first CPU node. The referenced property does not exist (the correct value is the default of 0), but this allows the follow-on init to complete. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move CPU init code into the driverSimon Glass2016-01-24-22/+4
| | | | | | | | | | | | | | | | Use the CPU driver's probe() method to perform the CPU init. This will happen automatically when the first CPU is probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Use common CPU init codeSimon Glass2016-01-24-52/+79
| | | | | | | | | | | | | | | | | | The existing ivybridge code predates the normal multi-core CPU init, and it is not used. Remove it and add CPU nodes to the device tree so that all four CPUs are set up. Also enable the 'cpu' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move GPIO init to the LPC init() methodSimon Glass2016-01-24-4/+3
| | | | | | | | | | | | | | This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move sandybridge init to the lpc probe() methodSimon Glass2016-01-24-17/+18
| | | | | | | | | | | | | | | | The watchdog can be reset later when probing the LPC after relocation. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move graphics init much laterSimon Glass2016-01-24-78/+76
| | | | | | | | | | | | | | | | We don't need to init the graphics controller so early. Move it alongside the other graphics setup, just before we run the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Probe the LPC in CPU initSimon Glass2016-01-24-3/+2
| | | | | | | | | | | | | | | | We can drop the explicit probe of the PCH since the LPC is a child device and this will happen automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Rename lpc_init() to lpc_init_extra()Simon Glass2016-01-24-3/+3
| | | | | | | | | | | | | | | | In preparation for adding an init() method to the LPC uclass, rename this existing function so that it will not conflict. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move LPC and PCH init into northbridge probe()Simon Glass2016-01-24-23/+24
| | | | | | | | | | | | | | Move more code into the northbridge probe() function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move northbridge init into the probe() methodSimon Glass2016-01-24-14/+21
| | | | | | | | | | | | | | | | Now that we have a proper driver for the nortbridge, set it up in by probing it, and move the early init code into the probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Add a driver for the bd82x6x northbridgeSimon Glass2016-01-24-0/+25
| | | | | | | | | | | | | | | | Add a driver with an empty probe function where we can move init code in follow-on patches. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: x86: Add a northbridge uclassSimon Glass2016-01-24-0/+17
| | | | | | | | | | | | | | | | Add a uclass for the northbridge / SDRAM controller found on some older Intel chipsets. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Rename bd82x6x_init()Simon Glass2016-01-24-3/+11
| | | | | | | | | | | | | | | | Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move more init to the probe() functionSimon Glass2016-01-24-43/+43
| | | | | | | | | | | | | | | | Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move lpc_early_init() to probe()Simon Glass2016-01-24-28/+26
| | | | | | | | | | | | | | | | Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Set up the LPC device using driver modelSimon Glass2016-01-24-1/+15
| | | | | | | | | | | | | | | | | | | | Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: pci: Convert bios_emu to use the driver model PCI APISimon Glass2016-01-24-8/+165
| | | | | | | | | | | | | | | | At present this BIOS emulator uses a bus/device/function number. Change it to use a device if CONFIG_DM_PCI is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: syscon: Allow finding devices by driver dataSimon Glass2016-01-24-12/+50
| | | | | | | | | | | | | | | | We have a way to find a regmap by its syscon driver data value. Add the same for syscon itself. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: usb: Add a compatible string for PCI EHCI controllerSimon Glass2016-01-24-0/+6
| | | | | | | | | | | | | | | | | | Add a compatible string to allow this to be specified in the device tree if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: core: Display the error number when driver binding failsSimon Glass2016-01-24-1/+2
| | | | | | | | | | | | | | | | This is often -96 (-EPFNOSUPPORT) which indicates that the uclass is not compiled in. Display the error number to make this easier to spot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: x86: Drop the weak cpu_irq_init() functionSimon Glass2016-01-24-17/+0
| | | | | | | | | | | | | | | | There are no callers now. Platforms which need to set up interrupts their own way can implement an interrupt driver. Drop this function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: x86: queensbay: Add an interrupt driverSimon Glass2016-01-24-39/+67
| | | | | | | | | | | | | | | | | | Add a driver for interrupts on queensbay and move the code currently in cpu_irq_init() into its probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: x86: quark: Add an interrupt driverSimon Glass2016-01-24-27/+51
| | | | | | | | | | | | | | | | | | Add a driver for interrupts on quark and move the code currently in cpu_irq_init() into its probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Drop the irq router compatible stringSimon Glass2016-01-24-2/+0
| | | | | | | | | | | | | | We use driver model for this now, so we don't need this string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-10 12:59:49 +0000